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Original question:

Bidirectional digital isolator for CAN

TINA/Spice/TIDA-01487: TIDA-01487

user3231337
Prodigy 40 points
Part Number: TIDA-01487
Other Parts Discussed in Thread: TINA-TI, SN7404, SN74HC08, SN74HC32,

Tool/software: TINA-TI or Spice Models

In TIDA-01487 schematic, the SN74LVC2G132DCTR, SN74LVC2G07DBVR, SN74LVC2G04DBVR, SN74LVC2G08DCUR and SN74LV32APWR are used for the bus arbitration logic. Could you tell me if we only use this bus arbitration logic in classical CAN(maximum speed is 1Mbps), not CAN FD, can I use the SN7404, SN74HC32 and SN74HC08 as schematic in design guide in our products? Thanks.

Best regards,

  • 0
    TI__Expert 4490 points
    We have used the LVC series because of the low propagation delay time within the logic gates to achieve the CAN FD speed of up to 5 Mbps. You are right, when using lower CAN speed you may can use alternative parts - assuming they match the voltage level - but we did not simulate it.

    For such purpose you can download the simulation files of the arbitration logic (they work with TINA-TI) and simulate alternative logic for lower CAN speeds.

    To access the simulation file, go to www.ti.com/.../TIDA-01487 and look here at the "Models" as well as the "Development Tools" at the bottom of the website.

    Regards,
    Thomas
  • 0 in reply to Thomas Mauer
    Prodigy 40 points

    Thank you Thomas.

    I downloaded the simulation file at the "Models" and simulated it, I found delay time of U8 is 180ns and U11 is 210ns. Why are they different?

    The second question is: According to the simulation waveform,  the purpose of CAN Bus Arbitration Logic Circuit is to prevent TX1 from transmiting dominant state(TX1 is 0V) when CAN bus entered the dominant state (the level of RX1/TX2 is 0V), is this correct? Thanks.

    Best regards,

  • 0 in reply to user3231337
    TI__Expert 4490 points
    About your questions on delay time: The TI design guide (www.ti.com/.../tidudb5a.pdf in section 2.4.3) actually shows two times 210 ns so I we made the delay time symmetrical finally. We had added the simulation files at a later time after we have published the TI design, hence we had tested different timings and this 30ns offset sneaked in.

    On your second question about the CAN bus arbitration logic. You are correct, the arbitration logic should prevent that either side will get stuck in the dominant state, because the CAN transceiver loop back the signal they are transmitting. So once the side which transmits a dominant state, this dominant state is looped back on the RX signal. The arbitration logic then blocks the looped back RX signal from reaching the initiator side.

    Regards,
    Thomas