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TIDA-010042: ADC access pins on MSP430F5132

bob young
Prodigy 75 points
Part Number: TIDA-010042

The TIDA-010042 reference design shows Load Current is measured on PJ.0 but the MSP430F512 data sheet does not show access to the internal ADC as an option for that pin. Per my data sheet, access to ADC channels is provided via P1.0 - P1.5, and P3.5 - P3.7. Perhaps a typo in one of these docs or I am misinterpreting something. Would one of you kind folks provide guidance here?

  • 0
    TI__Mastermind 49692 points

    Hi Bob,

    Thanks for posting your question on E2E. I downloaded the code for TIDA-01-0042, and I found in 'main.c' that it uses the comparator functionality of this pin, CB6. This approach is probably easier and more efficient than using the ADC since it's comparing the signal to a certain threshold.

    /* *************************************************************************************** *
 * Call this function to initialize the comparator for load current (L_I) monitoring       *
 *  Since over-discharge of the battery can shorten the expected battery life and lead to  *
 *  severe damage, the load needs to be disabled if overcurrent occurs                     *
 * *************************************************************************************** */
void Init_Comparator(void)
{
    CBCTL0 |= CBIPEN + CBIPSEL_6;   // Enable V+, input channel CB6
    CBCTL1 |= CBPWRMD_1;            // Normal power mode
    switch(Load_I_Limit & 0x03)     // Load current limit = .103125 * (CBREF + 1) / (Amp_Gain * Shunt_Resistance)
    {
        case 0x00:      // 5A -- actual 4.13A
            CBCTL2 = CBRS_1 + CBRSEL + CBREF1_3 + CBREF0_3;
            break;
        case 0x01:      // 10A -- actual 9.28A
            CBCTL2 = CBRS_1 + CBRSEL + CBREF1_8 + CBREF0_8;
            break;
        case 0x02:      // 15A -- actual 14.44A
            CBCTL2 = CBRS_1 + CBRSEL + CBREF1_13 + CBREF0_13;
            break;
        case 0x03:      // 20A -- actual 19.59A
            CBCTL2 = CBRS_1 + CBRSEL + CBREF1_18 + CBREF0_18;
            break;
        default: break;
    } // end switch
    CBCTL3 |= BIT6;             // Input buffer disable at PJ.0/CB6
    __delay_cycles(7500);       // Delay for the reference to settle
    CBINT &= ~(CBIFG + CBIIFG); // Clear any errant interrupts
    CBINT |= CBIE;              // Enable comparator B interrupt on rising edge of CBIFG
    CBCTL1 |= CBON;             // Enable comparator B
} // end Init_Comparator

    Regards,

    James

  • 0 in reply to James Evans
    Prodigy 75 points

    James,

    Thanks for clearing that up!

    by

  • 0 in reply to bob young
    TI__Mastermind 49692 points

    Happy to help, Bob. Have a great day!

    Regards,

    James