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Original question:

LMK04828: No clock output past a certain divider value

LMK04828: Clock output problems for low frequency.

bilgin vargun
Prodigy 20 points
Part Number: LMK04828

Hi, 

We can program clk outputs 1Ghz to 2.4 Ghz but, we have no clk output less then 800 Mhz.

Thanks

  • 0
    TI__Mastermind 24205 points
    Hi,

    Please provide details of your .tcs configuration?

    Regards
    Arvind Sridhar
  • 0 in reply to Arvind Sridhar
    Prodigy 20 points

    clock_data_22112018_100mHZ.txt 
    R0 (INIT)	0x000090
R0	0x000010
R2	0x000200
R256	0x010003
R257	0x010155
R259	0x010301
R260	0x010402
R261	0x010500
R262	0x0106F1
R263	0x010700
R264	0x01080C
R265	0x010955
R267	0x010B00
R268	0x010C02
R269	0x010D00
R270	0x010EF1
R271	0x010F00
R272	0x011001
R273	0x011155
R275	0x011300
R276	0x011402
R277	0x011500
R278	0x0116F9
R279	0x011710
R280	0x011801
R281	0x011955
R283	0x011B00
R284	0x011C02
R285	0x011D00
R286	0x011EF9
R287	0x011F01
R288	0x01200C
R289	0x012155
R291	0x012300
R292	0x012402
R293	0x012500
R294	0x0126F9
R295	0x012711
R296	0x012808
R297	0x012955
R299	0x012B00
R300	0x012C02
R301	0x012D00
R302	0x012EF9
R303	0x012F00
R304	0x013018
R305	0x013155
R307	0x013301
R308	0x013402
R309	0x013500
R310	0x0136F1
R311	0x013711
R312	0x013805
R313	0x013900
R314	0x013A0C
R315	0x013B00
R316	0x013C00
R317	0x013D08
R318	0x013E03
R319	0x013F00
R320	0x01400F
R321	0x014100
R322	0x014200
R323	0x014331
R324	0x014400
R325	0x01457F
R326	0x014618
R327	0x01471A
R328	0x014802
R329	0x014942
R330	0x014A02
R331	0x014B16
R332	0x014C00
R333	0x014D00
R334	0x014EC0
R335	0x014F7F
R336	0x015003
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x015478
R341	0x015500
R342	0x015678
R343	0x015700
R344	0x015896
R345	0x015904
R346	0x015AB0
R347	0x015BD4
R348	0x015C20
R349	0x015D00
R350	0x015E00
R351	0x015F0C
R352	0x016000
R353	0x016101
R354	0x016244
R355	0x016300
R356	0x016400
R357	0x01650C
R380	0x017C15
R381	0x017D33
R358	0x016600
R359	0x016700
R360	0x01680C
R361	0x016959
R362	0x016A20
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E14
R371	0x017300
R8189	0x1FFD00
R8190	0x1FFE00
R8191	0x1FFF53
    clock_data_22112018_2400mHZ.txt 
    R0 (INIT)	0x000090
R0	0x000010
R2	0x000200
R256	0x010003
R257	0x010155
R259	0x010301
R260	0x010402
R261	0x010500
R262	0x0106F1
R263	0x010700
R264	0x01080C
R265	0x010955
R267	0x010B00
R268	0x010C02
R269	0x010D00
R270	0x010EF1
R271	0x010F00
R272	0x011001
R273	0x011155
R275	0x011300
R276	0x011402
R277	0x011500
R278	0x0116F9
R279	0x011710
R280	0x011801
R281	0x011955
R283	0x011B00
R284	0x011C02
R285	0x011D00
R286	0x011EF9
R287	0x011F01
R288	0x01200C
R289	0x012155
R291	0x012300
R292	0x012402
R293	0x012500
R294	0x0126F9
R295	0x012711
R296	0x012808
R297	0x012955
R299	0x012B00
R300	0x012C02
R301	0x012D00
R302	0x012EF9
R303	0x012F00
R304	0x013018
R305	0x013155
R307	0x013302
R308	0x013402
R309	0x013500
R310	0x0136F1
R311	0x013711
R312	0x013805
R313	0x013900
R314	0x013A0C
R315	0x013B00
R316	0x013C00
R317	0x013D08
R318	0x013E03
R319	0x013F00
R320	0x01400F
R321	0x014100
R322	0x014200
R323	0x014331
R324	0x014400
R325	0x01457F
R326	0x014618
R327	0x01471A
R328	0x014802
R329	0x014942
R330	0x014A02
R331	0x014B16
R332	0x014C00
R333	0x014D00
R334	0x014EC0
R335	0x014F7F
R336	0x015003
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x015478
R341	0x015500
R342	0x015678
R343	0x015700
R344	0x015896
R345	0x015904
R346	0x015AB0
R347	0x015BD4
R348	0x015C20
R349	0x015D00
R350	0x015E00
R351	0x015F0C
R352	0x016000
R353	0x016101
R354	0x016244
R355	0x016300
R356	0x016400
R357	0x01650C
R380	0x017C15
R381	0x017D33
R358	0x016600
R359	0x016700
R360	0x01680C
R361	0x016959
R362	0x016A20
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E14
R371	0x017300
R8189	0x1FFD00
R8190	0x1FFE00
R8191	0x1FFF53
    Hi Arvind,

    I attached 2 files. 2.4GHz and 100 MHz configurations. I can observe 2.4 GHz clock signal but cant 100 MHz. I use same port. Also I have tried other ports for same files, result is same. 2.4 GHz configurations run in Bypass mode.

    In  our design there are 6 clock outputs (not sysref) Whenever I use bypass mode for all of them I can observe 2.4GHz clk . For higher division values I couldn't observe.

  • 0 in reply to bilgin vargun
    TI__Mastermind 28540 points
    Hello,

    I think you may be holding your outputs in SYNC. Try changing the SYNC_POL bit or the state of your SYNC input pin.

    Also, can you confirm results when toggling SYNC (meaning SYNC off, SYNC on, SYNC off).

    73,
    Timothy