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LMX2541SQ2690ENOPB design review

Other Parts Discussed in Thread: LMX2541, LMX2572LP

Hi,

LMX2541SQ2690E.pdfPlease review the attached LMX2541SQ2690ENOPB design.
This clock synthesizer is used for generating the ADC sampling clock frequency of 1350MHz of required input level of maximum 2Vp-p, 0.4Vp-p minimum and 0.6 Vp-p is typical.

Please verify and provide the comments if anything is missed and wrong.

Thanks & regards,
Divya

  • Hi Divya,

    Your DC resistance to the XO is less than 40Ω, I don't think your XO is able to drive this load.

    My suggestion is remove R233; change R497 to 100nF and then change R231 to 50Ω.

    RFout is not 50Ω, you may need to enable the T-pad between C514 and C594.

  • Hi Noel Fung,

    Thanku for the suggestion.

    As suggested, removed R233, replaced R497 with 100nF and changed R231 to 50R resistor.

    Can i know What is the purpose of  replacing the  R497 to 100nF  and R231 & R234 will act as divider network to the OSCIN pin. then the signal level will be divided by half.

    And also we enabled T-Pad between C514 & C594 and values are R236 =10R, R499=470R, R498=10R. Is is the correct values for 50R impedance ?

    We have selected 100MHZ HCMOS oscillator XLH736100.000000 for generating the reference frequency to LMX, Is this part meets the Phase Noise Requirement ?
    Phase Noise : -100dBC@1KHz, -110dBC@10KHz and -120dBc@100KHz

    And selected oscillator part  generates square wave, is it fine ? We used switching regulator to Power on the LMX  clock synthesizer  & Regulator part no: LMZ31707RVQR. can i power on LMX with switching regulator ? 

    Also please provide the slew rate sensitivity data for OSCIN at all frequency ranges. 

    Thanks & regards,

    Divya

  • Hi Divya,

    The 100nF is to avoid DC current flowing to the 50Ω load. 

    A CMOS XO expects a high impedance and small capacitance load. With an AC-coupled 50Ω load, we usually see the output swing will drop to 2Vpp. R231 and R234 can be a real voltage divider if their values are 10k and 50kΩ. 

    If R499=120Ω, then it becomes a 3.5dB 50Ω T-pad. There are online calculators as well as appnotes on the T-pad and π-pad, do a google search can get other attenuation values in a minute. 

    The phase noise of your XO is not pretty good, but good or not depends on your system requirement. If your system cares the phase noise at 1kHz offset, maybe you will need a better phase noise XO. 

    A square wave reference clock is good for a PLL. Usually PLL's noise will be smaller with a high slew rate reference clock.

    LMX works with DC/DC supply as the LMX device has internal LDO. However, it is still suggested to make the DC/DC noise as small as possible.

    I am afraid we don't have slew rate sensitivity data for OSCin.

  • Hi Noel Fung,

    How R231 & R234 act as voltage divider if it is 10K & 50K ?
    How phase noise of the oscillator is depends on the system requirement, phase noise of the oscillator is -100dBC@1KHz is it not good ?
    Then what is the required phase noise. can u explain it.

    Thanks & regards,

    Divya

  • Hi Divya,

    We should have the system requirement before we can select the right building block components to fulfill the requirement.

    If you can tell me your system requirement on phase noise, we could provide suggestion on TI parts.

  • Hi Noel Fung,

    Please find the below phase noise requirement for Output clock frequency of 1350MHz.

    -100dBc @1KHz,
    -110dBc@10KHz,
    -120dBc @100KHz

    Please provide the suggestion.

    Thanks & regards,

    Divya

  • Hi Divya,

    -100dBc @1KHz, --> your 100MHz XO should has phase noise better than -112.6dBc
    -110dBc@10KHz,
    -120dBc @100KHz --> LMX2541 can marginally meet this requirement. You may need to consider LMX2572LP, it can give you a few more dB margin.

    BTW, please use PLL Sim to design your loop filter and also estimate which TI part can meet your requirement.