LMK61E2: LMK61E2 - very large frequency error.

Hi,

I have tried register map You have provided, it also provides large frequency error. As a further research, among other things i have checked by hand registers generated via LMK programming tool (they gave mi proper frequency values on paper) and tried setting manually calculated registers, but they also produced large error in measured output

However, when I have imputed slightly offset frequency into LMK programming tool (196.60799MHz instead of 196.608MHz), resulting registers gave mi valid output frequency measured at 196.605338MHz, which is within 13.5ppm of target and perfectly acceptable for my system even including measurement errors. After experimenting a little more, I have noticed that frequency inputs with added very small fractional offset produce valid outputs, even if both them and "normal" inputs produce register settings that seems valid. The only common difference in register values i have observed is much larger NUM and DEN values generated in such cases. Is there any known issue with accuracy of the LMK61E2 fractional divider?

I have been also experimenting with XO_CAPCTRL register and tuning it, but any changes made here have not produced frequency frequency difference anywhere near 1%,

As for LOL bit, i have been checking it all the time and it always stayed at 0 after programming finished.

Best regards,

Hi Dawid, 

Which registers did you specifically program? Since VCO frequency, Ndiv are getting updated, the VCO needs to re-calibrate, so without issuing a PLL reset it will not update. Toggle R72[1] which should be self clearing. 

Speaking of which I noticed in the first readback you provided R72[1] is already high, this should self clear.. without this clearing PLL will be held in reset.. so I'm confused what's happening.. 

The EEPROM factory configuration that comes up at 156.25 MHz that you mentioned had 0.00134% error, what is R72 readback in this condition. Also, how about other case that you mentioned programming 196.60799 MHz. 

Regards, Amin 

Hi Amin,

The register values i have attached are not readback from the LMK61 device, but raw register map generated by the Programming Tool. I have also trying omitting RESERVED and XOCAPCTRL registers during upload with no results.

Usually, I am just uploading all register values staring with R0 and ending at R72. Hence, PLL reset is issued.

After upload I am checking R72[1], R66[0] and R66[1] to make sure everything is properly initialized, all those bits are clearing to proper values.

Best regards,

Hi Dawid, 

If the frequency error from the configuration that Hao provided to the one you generated in the initial post the same? 

In both cases, can you confirm the registers are actually being updated? I would suggest just check a few of them, like R22 - R26, to confirm they're indeed being updated. 

When you mention generating 196.60799 works without an issue, do you observe any differences between that readback vs 196.608 version? Not vs each other but rather from what's generated by the GUI and what actually gets readback. 

Lastly, this is all on one device, correct? 

Regards, Amin

Hi Amin,

Sorry for late response, I was busy with another project.

I have performed verification and all relevant registers are being updated properly - readback from the LMK device is 100% correct in all cases.

I have resoldered LMK61 to another unit and got same results. Both were ordered directly from TI Store.

Best regards,

Hi Dawid, 

We will be trying this on the bench to see if we can reproduce what you have observed. I will have an update to you by the end of the week  5/29. 

Regards, 

Amin 

Hello, 

So I'm not sure I understand what is happening here... 

We have tried this on the bench. Used the LMK61E2 device and the TICspro GUI and produced the correct output. Just typing in 196.608 in the output configuration frequency box and clicking generate configuration produced correct results. 

For 196.608 MHz configuration we measured around 196.6071x. This equates to ~5 ppm error. We programmed eeprom and did multiple power cycles, with no issues. 

I don't know whether original image (in the first post) is still the valid one but as Hao mentioned there are major differences from that and what the GUI generates, for example the VCO frequency. How did your GUI arrive at 5561.024 MHz? It should generate generate the configuration Hao provided. 

Secondly, looking at R72 being 02, I can already confirm a read all registers wasn't performed. R72 goes to 0x02 to recalibrate the VCO but it self clears. We have confirmed this on the bench, after generate configuration and saving raw registers, you will see R72 at 0x02 while performing a read all and then saving registers, you will see R72 has already cleared to 0x00. So my concern is if no read all is perform the registers may not have been updated as presumed. 

Regards, Amin