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Welcome everybody. It's my first post here.
I'm about to to connect my Sony FCB-SE600 to Tegra 3 module.
Sony output: 1 x CLK + 4 x Data differential lanes, Y/Pb/Pr 4:2:2 (LVDS) (y:8bit, C: 8bit, Vsync, Hsync, Field, Clock). On every CLK pulse there are 7 Data pulses what gives 4 x 7 = 28 data bits: 24(pixel color) + 4(sync). I think it is FlatLink. http://www.sony.co.jp/Products/ISP/support/manual/FCB-SE600_TM_E.pdf
Tegra input: CSI-2 or 8-bit YUV digital I/F with external or embedded syncs (ITU601, ITU656)+HSYNC+vSYNC+PIX_CLK
My wish is to send FullHD frame: 1920x1080@30fps= 186 MB/s
HD(1280x768) resolution will also works for me.
I cant find one dedicated chip to make this conversion so firstly I'm going to use DS90CF386 to convert Sony's LVDS to 24 parallel+SYNC. My concerns are about throughput. 386's datasheet says "SXGA(1280x1024)" and later: "Up to 2.38 Gbps throughput or 297.5 Megabytes/sec bandwidth). My calculation gives me 186 Mbytes/sec for FullHD. Can You give me formula how to calculate real throughput for 386 or confirm if FullHD@30fps is supported?
Next I'm going to build dedicated FPGA module to conver 24bit parallel to 8bit parallel or do you recomend any dedicated chip to conver 24bit to 8bit or CSI-2 ?
Second scenario is to use DS90UH927Q: Sony(LVDS)->DS90UH927Q(FPD-Link III)->DS90UR910-Q1(CSI-2)->Tegra Bottleneck here is 910. Only 75Mhz. Can you tell what is max resolution @ 30fps for this chip?
Can you tell will it work?
