I've actually solved my problem with the LMH1982 eval kit software. Here's what worked for me. The whole process is free and took less than 15 minutes.
I installed Virtual Box on my Windows 10 computer.
I downloaded the "IE11 on Windows 7" image…
Other Parts Discussed in Thread: LMH1982 , LMH1981 Hi,All
I am using lmh1982 with lmh1981 for video system design. There is one trouble block me for a long time. I list the problem and test result from my debug process as followed.
The lmh1982 is…
Other Parts Discussed in Thread: LMH1982 , LMH1981 Hi,All
I am using lmh1982 with lmh1981 for video system design. There is one trouble block me for a long time. I list the problem and test result from my debug process as followed.
The lmh1982 is…
Other Parts Discussed in Thread: LMH1983 , LMH1982 Hello!
For a quick start-up please help to understand obvious and not so obvious differences between LMH1983 and LMH1982, besides that LMH1983 supports audio and LMH1982 does not.
With best regards…
Other Parts Discussed in Thread: LMH1982 We have an application where the differential clock outputs of LMH1982 are running into Si5324 clock part. Can someone recommend a termination impedance?
Regards,
-Jaden
Why does the LMH1982SQEEVAL board bring up the 2.5v rail before the 3v? This is the opposite of what the datasheet says to do. Should we follow the datasheet or the eval board?
-Jaden
Other Parts Discussed in Thread: LMH1982 Please tell me how LMH1982 detects H_ERROR.
When (Hsync input / reference divider) and (VCXO clock / feedback divider) has phase error, there should be some "threshold" or "Time Window" for LMH1982 to decide…
Hi Alan,
I understand from the data sheet that there is a suggested sequence that the registers should be programmed.
Is there a way of showing the sequence and register values that are generated when using the LMH1982 Application v2.0 program without…
I understand the "LOCK_CTRL" (Register 01h) programs the maximum phase error between PLL1's Phase Detector inputs.
Is the allowable phase error set by LOCK_CTRL based on (Hsync input / reference divider) or (VCXO clock / feedback divider) ?
I am…