OPA392: Accurate measurement of voltage from high impedance source

Tomasz,

One thing you need to be aware of is that since the output of an op amp cannot swing all the way to its rails, in a single supply operation you need to apply a small negative voltage to enable Vout to get to the system ground. OPA392 AOL specification shows 50mV to 100mV (for 2k vs 10k load, respectively) linear output swing to the rail - see below.

Since I could not open you files, I created Tina-TI schematic, which I believe you use to gain up your input signal.  However, in order to assure a linear operation of OPA392 output stage for zero input signal, I have added 100mV negative supply Voltage - see below.

Fig 1 shows Vos1 of -21.5uV, which after a gain of 300 correctly show Vout1 of -6.4mV.  Likewise, Fig 2 shows 49.2uV, Vin, drop across 10M input resistor (4.9pA*10M) resulting in Vos2 of 27.7uV (49.2uV-21.5uV).  Gaining it up by 300 correctly show Vout2 of 8.3mV - see below.  Thus, the output error you see is the input offset voltage gained up by 300.

Sweeping the VG1 input from 0 to 10mV, properly shows the output voltage changing from around zero to 3V - see below.

Tomasz OPA392 circuit.TSC

Hi Marek Lis, thank you for your response. My test design takes output swing headroom to negative supply into consideration. The signal ground is 30mV above the OpAmp negative power supply but, as you pointed out, it should probably be increased to 100mV - I was looking at the OUTPUT specs section only.

However, what surprised me was input current much higher than expected - almost 5pA - while specs show input bias current and input offset current 0.01pA (typ). Do I misinterpret those numbers? Perhaps I do.

Links to images and TINA file I attached take about 15s to load but eventually they show up.

Hi,

here is Thomasz's simu file:

tomasz_opa392.TSC

Kai

kai klaas69, thanks! I have updated my initial post once I figured out files could be simply dragged and dropped.

Dzięki Marek! That makes a lot of sense. Indeed, increasing Vref to 2.5V causes Vout drop from 7 to 0.3mV.
OPA392 may not be the best choice for this job. I did not realize I_B stays low only within rather narrow range of common voltage.
LMP7721 appears to be far better choice, LMP7715 being second choice.
I start to think that I need two-stage amplifier. First stage with low I_B/I_OS and low gain, second with low V_OS and high gain. LMP7721 has significantly higher V_OS, which I do not want to get amplified.
What do you think? How would you approach such challenge?

I did not mention that gain needs to be programmable, at least 4 ranges, TMUX1104 seems to a good choice thanks to its low leakage but any additional elements in such sensitive circuit will pick up lots of EMI/RFI. This is another reason why I think two-stage architecture may be a better choice.

Update: LMP7721 TINA simple simulation does not yield great results either (I_B=2.9pA @ V_CM=1.5V). This I_B is an order of magnitude higher than what I was hoping to obtain. What am I missing?

LMP7721 - test 1.TSC

Tomasz,

You may not rely on the LMP7721 macromodel to show correctly IB at fA range - instead you need to look at the specifications below. 

IB stays flat at few fA for as long as Vcm <(V+)-2V - see below.  This means that despite what the simulation shows under the conditions shown above, IB should stay below +/-20fA at 25C.

Having said that, any increase in ambient or junction temperature will increase IB.  For this reason, the way to make this work is to calibrate the system - this means you need to measure the output voltage for 0mV input signal and then account for it while measuring any other DC input voltage from 0 to 10mV.

Marek, what I am trying to accomplish is a design which does not need such calibration and is still precise enough. Precise enough in my case means 0.1%. Such precision would be more than satisfactory and I still hope this is achievable. It does not need to keep params within wide temp range.

I will give LMP7721 a shot. I think TI should consider updating the model since it is highly inaccurate with respect to the most prominent feature of this product.
Do you think two stage architecture makes sense in this case? The down side of LMP7721 is its relatively high V_OS I do not want to get amplified.

Accurate model would help a lot to play around. Thank you for the help and clarification.

I may be able to use 5MΩ signal source and accuracy >0.25% may be acceptable so I think this design has some chance to fly.
I may also use OPA387 instead OPA392. It has much lower V_OS within the entire V_CM range. See screenshot below.
Again, thanks a lot!

One more comment to those who may come across this thread.
What I initially failed to notice was that, according to docs, OPA392 maintains low I_B (-20/+30fA) within V_CM=±1.5V range (is it relative to V_S/2 ?) and above V_CM=1V I_B+ goes through the roof. The available TINA-TI models for both OPA392 and its sibling OPA397 do not seem to reflect it correctly. This is probably a topic for another thread.

So maybe OPA392 in my two-stage design could be used as a buffer as well? Its I_B is not as low as LMP7721's but it may be low enough. Note that increased, non-linear I_B zone (circled in orange) is present at lower V_CM end as well. To avoid this range I should probably set Vref at 200-300mV (rather than 20-30mV specified in characteristics OUTPUT section) to keep I_B low and linear. Too bad specs contain no such diagram for Vs=5V, only for 1.7 and 3.3V while to be effectively used with a standard 2.5-3V ADC in such scenario those OpAmps should be powered from 5V.

Tomasz,

I previously showed OPA392 graph of IB vs Vcm for Vs=5.5 (see Fig 6-13 below), which shows a large IB hump (>60pA) for higher supply voltage but not for Vs of 3.3V.  For lower supply voltage, there is no large (>30fA) "increased, non-linear I_B zone (circled in orange) present at lower V_CM" UNTIL Vcm is above or below supplies (+/-1.65V) - this makes a perfect sense since at this point ESD protection diodes get forward-biased.  Perhaps you could use OPA392 for your solution for as long as you use a lower supply voltage (Vs=<3.3V).

Now I got it. I do not why I could not see it before. Thank you for your patience.
Is it safe to assume that I_B+ bump starts at V_CM=3.75V regardless of V_S? That means, as long as V_S (and V_CM) stay below 3.75V, I_B+, bump does not show up at all. It may be important to know the general rule because I am going to use standard V_S=5V, not 5.5V.

Tomasz,

Based on the above graphs of OPA392 IB vs Vcm, it is safe to assume that there is no large I_B+ bump below V_CM <(V+)-2V regardless of Vs. Thus, in order to avoid the bump for Vs=5V single supply, the input common-mode voltage must be: V_CM < 3V.  Also, there is no  I_B+ bump across entire Vcm if Vs<3.3V

Proper interpretation of Figure 6-13 is critical in my scenario - V_CM may change in 0-3.0V range. Thank you for the confirmation, it seems I should be fine.

You're welcome. Good luck. Powodzenia!