OPA830: Sallen-key LPF output oscillation

Follin Ju

Part Number: OPA830

Hello,

I'm designing a sallen-key LPF. The output seems has some oscillation, and the oscillation is always near 0V to DC-bias (above is the input signal and below is the filtered signal).

The oscillation is aournd 50MHz, 110mVpp

I know there's high frequency feed through issue with active filters, but I assume if this is the cause, th oscillation shall not be fixed on the same position (or the noise is always keep same phase???).

Anyone who can help explain it? Thanks!

Simulation is shown below:

over 1 year ago

0 kai klaas69 over 1 year ago

Guru 140200 points

Hi Follin,

this filter looks very strange because R4 is way too small. Increase R4 and decrease C6.

Also, C3 is in the same order as the input capacitance of OPAmp which results in a big error of filter curve. Increase C3 and decrease R5.

Best you use a filter topology which has R4 = R5. Here's a nice appnote:

sboa226.pdf

Kai

0 Follin Ju over 1 year ago in reply to kai klaas69

Prodigy 195 points

Hi Kai, thank you so much for the quick reply all the time. I will try different resistor/capacitor value. But I'm still a bit wondering which parastic capacitor causes this compared with the simulation one.

0 Michael Steffes over 1 year ago in reply to Follin Ju

Guru 48165 points

what is your load, don't probe with a 10pF scope, probe on the other side of a 100ohm iso R.

0 Follin Ju over 1 year ago in reply to Michael Steffes

Prodigy 195 points

The load is a differential opamp with Rg=Rf=499Ω, I used coaxial wire with BNC connected to scope.

0 Follin Ju over 1 year ago in reply to kai klaas69

Prodigy 195 points

And also want to know why the oscillation only occur around 0 to dc bias voltage.

0 Follin Ju over 1 year ago in reply to Michael Steffes

Prodigy 195 points

I've tied a 100ohm iso R and it works! Why will a 10pF cap cause this issue? I assume it's related to the gain peak when a C_load connected....

+1 kai klaas69 over 1 year ago in reply to Follin Ju

Guru 140200 points

Hi Follin,

yes, the 10pF is the issue, as Michael already mentioned. The directly mounted 10pF cap causes instability by eroding the phase margin:

follin_opa830.TSC

Take my simulation and run a phase stability analysis after inserting the 100R isolation resistor

More on stability can be learned from the TI's training video series on stability:

training.ti.com/.../1138805

Kai

0 Follin Ju over 1 year ago in reply to kai klaas69

Prodigy 195 points

Great! I was also looking into how to test the phase margin and your simulation pasted is very clear, thanks!

0 kai klaas69 over 1 year ago in reply to Follin Ju

Guru 140200 points

Happy to help

Kai

0 Follin Ju over 1 year ago in reply to kai klaas69

Prodigy 195 points

Hi Kai,

I'm familiar with stability simulation with normal amiplication circuit - usually break the feedback loop and insert L/C/source to simulate. But I'm not clear about both IN+/IN- loop disconnection as you posted. I think I haven't seen it in the stability course. Is there any related article/course? Thanks in advance.