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PGA113: Suitable PGA for the system?

Emanuel Soares
Intellectual 530 points
Part Number: PGA113
Other Parts Discussed in Thread: OPA320, OPA357, ADS7945, ADS7946

Hello to whom this may concern,
This is the description of the situation:
1. Input ignal: The system need to be able to capture two types of signal (from a BLDC or PMSM motor phase), and for each type the signal can vary its amplitude as shown:
    * Sinusoidal: Max Vpp = 60V with zero offset and min Vpp = 6V with zero offset;
    * PWM of max frequency 200kHz: Max amplitude = 60V and min amplitude = 6V, all with min level ideally at 0v.
Both signals are represented below:

2. ADC: 12bit with sampling rate of 0.5uS (Max desirable).

To make possible to treat the signal, the following circuit is proposed:


Knowing all of this, we have some questions:

1. What would be the real closed-loop BW of this system for PGA gain 1 to 10 ?
2. Is this real closed-loop BW compatible with the 12 bit ADC @ 0.5uS sampling rate ?

  • 0
    TI__Expert 8055 points

    Hi Emanuel,

    I notice a few things about your proposed circuit and I have a few questions and suggestions...

    What is the frequency range of your input signal? I see the maximum is 200kHz. What is your desired attenuation from your voltage divider at these frequencies?

    Your input voltage divider seems to be configured for a gain of -27dB at DC. However at AC the attenuation is much greater due to the R55.

    Also the -3dB point of the high pass filter is at ~37kHz. Depending on your minimum input frequency, your input signal may be attenuated much more than anticipated.

    Increasing R55 to 10x R28 will reduce the additional voltage divider effect, and increasing C123 will allow slower AC signals to pass while rejecting the DC.

    Emanuel Soares said:
    1. What would be the real closed-loop BW of this system for PGA gain 1 to 10 ?

    Table 8 in the PGA113 datasheet shows the -3dB bandwidth for various gains.

    Emanuel Soares said:
    2. Is this real closed-loop BW compatible with the 12 bit ADC @ 0.5uS sampling rate ?

    The settling time shown in Table 8 implies that the PGA113 can drive a 12-bit ADC up to ~500 ksps. To drive your 2 Msps ADC, you may include an additional buffer stage using a higher bandwidth op amp such as the OPA320. What ADC are you using?

    See the simulation below. Note that I used ideal opamp for the PGA gain stage as there is no Spice model.

    PGA113_OPA320.TSC

    This circuit will work well for your sine wave input, however the slew rate of the PGA113 at a gain of 1V/V may not be enough for your PWM depending on the amplitude and frequency.

    The required slew rate for a sine wave is defined by the formula, SR = Vpeak*2π*f

    For your input voltage of ~1.3 Vpeak at 200kHz, the required slew rate is ~1.6V/μs which is satisfied by the PGA113 in a gain of 1V/V.

    However, a square wave typically requires 5-10 times the slew rate of a sine wave for acceptable performance.

    This means that in the gain of 1V/V your maximum frequency for PWM is ~73kHz.

    Are you expecting an input PWM signal of >73kHz at 60Vppk?

    Thanks,

    Zach

  • 0 in reply to Zach Olson
    Intellectual 530 points

    Hi Zach, sorry for the late reply.
    In order to answer your questions, consider:

    Zach Olson said:
    What is the frequency range of your input signal? I see the maximum is 200kHz. What is your desired attenuation from your voltage divider at these frequencies?

    A: The goal is to capture a voltage as close as possible to 3 Vpp at the output of the PGA. The role for the PGA is to mitigate the precision loss when we have lower voltage (6 vpp) at the input of the system, allowing the ADC at the output of the PGA to catch a desired 3vpp waveform (square or sin).

    Zach Olson said:
    The settling time shown in Table 8 implies that the PGA113 can drive a 12-bit ADC up to ~500 ksps. To drive your 2 Msps ADC, you may include an additional buffer stage using a higher bandwidth op amp such as the OPA320. What ADC are you using?

    A: we are going to use the ADS7946SRTER as ADC.

    After analyzing what you said, to mitigate some downsides of the capacitor in the system, we decided to change a bit the schematic, as it follows:




    In this case for the new schematic, the limitation for the PWM wave keeps 73kHz?

    Zach Olson said:
    Are you expecting an input PWM signal of >73kHz at 60Vppk?

    A: as this circuit will be used for motor caracterization, at 60vpp the frequency tends to be lower. But the desired frequency for the whole voltage range (6vpp to 60vpp) would be 200khz.

    best regards,
    Emanuel

  • 0 in reply to Emanuel Soares
    TI__Genius 11645 points

    Hi Emanuel,

    Zach is out of the office today, and e2e will undergo maintenance tomorrow.  We will have to get back to you on Monday.

    Regards,
    Mike

  • 0 in reply to Emanuel Soares
    TI__Expert 8055 points

    Hi Emanuel,

    I see you have removed the AC coupling capacitor from the input path. As your input signal is centered around 0V, this will cause the input to the PGA to go below the common-mode input range. Also, you are attenuating the input source much more than necessary with these resistor values.

    You may refer to the circuit below which meets your input/output range requirements. 

    Emanuel Soares said:
    In this case for the new schematic, the limitation for the PWM wave keeps 73kHz?

    73kHz is not a strict limitation, this is based on the guideline that a square wave require 5-10 times the slew rate as a sin wave of the same frequency (see my previous response). Your max PWM frequency depends on your specific performance requirements.

    Here I used a generic op amp model with a slew rate of 3V/μs to simulate the slew performance of PGA113 in a gain of 1V/V. As you can see, the output square wave is slew limited. You can decide if you are able to resolve this output signal with acceptable performance.

    Emanuel Soares said:
    we are going to use the ADS7946SRTER as ADC

    This is a 14-bit 2Msps ADC. According to the Analog Engineer's Calculator, this requires an op amp with a minimum of ~60MHz bandwidth to drive. The PGA113 is not fast enough to drive this ADC at the max sampling rate. I see you are already using the OPA357 to drive one of the ADC inputs. There is a dual version OPA2357 which will provide an extra channel you can use to buffer the output of the PGA113.

    By the way, some odd things about your schematic footprint for ADS7946. It appears to use the pin labels for the differential version (ADS7945) instead of the single-ended version (ADS7946), see below.

    There also seems to be an extra pin (pin 17) on your footprint labeled EP. The ADS7946 comes in a 16-pin package and there is no EP pin.

    Regards,

    Zach

  • 0 in reply to Zach Olson
    Intellectual 530 points

    Hi Zach,

    Zach Olson said:
    I see you have removed the AC coupling capacitor from the input path. As your input signal is centered around 0V, this will cause the input to the PGA to go below the common-mode input range.


    A: Plase consider also the correction for the R59 connection to the AVREF not to the PVC_REF:




    The removed capacitor is to avoid a high pass behave, as the max signal frequency would be 200kHz. In case of using the capacitor as you proposed, would this achieve a good bw?

    Zach Olson said:
    Also, you are attenuating the input source much more than necessary with these resistor values.

    A: What you meant by "attenuation the input source much more than necessary"?

    Zach Olson said:
    this will cause the input to the PGA to go below the common-mode input range

    A: Sorry for not mentioning, but we intend PVC_REF value to be variable, so should this work?


    Zach Olson said:
    There also seems to be an extra pin (pin 17) on your footprint labeled EP. The ADS7946 comes in a 16-pin package and there is no EP pin.

    A: You're right, the ADS has a wrong footprint, but in the datasheet you can see the image below:
     

     
    There's indeed a kind of thermal pad, at least for what the datasheet says. Should I put this pin 17?

    Best regards,

  • 0 in reply to Emanuel Soares
    TI__Expert 8055 points

    Hi Emanuel,

    Emanuel Soares said:
    A: Plase consider also the correction for the R59 connection to the AVREF not to the PVC_REF:

    Thanks for the clarification, with this node connected to 3.3V, the DC reference to the inverting terminal is larger than the DC input voltage at the non-inverting terminal. In a gain of 10 V/V, this causes the output of the simulated ideal amp to go negative, which implies that the output swing of the PGA113 will be violated. See below.

    Emanuel Soares said:
    The removed capacitor is to avoid a high pass behave, as the max signal frequency would be 200kHz. In case of using the capacitor as you proposed, would this achieve a good bw?

    The purpose of the high-pass filter is to block the DC common-mode input voltage in order to apply a set common-mode input voltage that is appropriate for the PGA113 device. See below the frequency response of the high-pass and voltage divider input circuitry. Note that the DC component is removed and the higher frequency signals around 200kHz are unaffected. 

    A large AC coupling capacitor such as the 10μF cap shown is necessary to allow the lower frequency components of the PWM signal to pass as well. See below that the PWM signal is passed through the input high-pass filter without distortion.

    Emanuel Soares said:
    A: What you meant by "attenuation the input source much more than necessary"?

    For best performance, it is undesirable to attenuate more than necessary as this will reduce your signal to noise ratio (SNR). I recommend sizing your input voltage divider to produce your desired ~3Vpp input signal when the largest input signal (60Vpp) is applied.

    Emanuel Soares said:
    Sorry for not mentioning, but we intend PVC_REF value to be variable, so should this work?

    I recommend following the circuit shown above with the input AC coupled and the PVC_REF as the DC bias for the amp. This will prevent unexpected output swing violations as PVC_REF is changed. See negative output swing example above.

    Emanuel Soares said:
    There's indeed a kind of thermal pad, at least for what the datasheet says. Should I put this pin 17?

    You are correct, there is a thermal pad and it is appropriate to label as pin 17.

    Regards,

    Zach