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Original question:

BUF634A: Max voltage in single supply configuration

BUF634A: BUF634AIDR delayed start up/output time

Dan Rebello
Prodigy 10 points
Part Number: BUF634A
Other Parts Discussed in Thread: BUF634

Tool/software:

Greetings,

I am testing BUF634AIDR as a replacement/upgrade for the obsolete OPA633KPG4. I currently have a prototype SMT-to-TH adapter board built: BUF634AIDR, 0.1uF caps on rails, and 10ohm resistor on BW adjust, TH pins to interface with legacy design CCA. I am seeing two issues, one of which I believe I know how to resolve, the other is this: there is an incredibly long time delay between power on and getting an output from the chip, approaching ~1min. I suspect there is a power issue, but I have not been able to determine the root cause..

The existing/legacy CCA (footprint for OPA 633) has +/-12V on the rails (within spec), and there two 0.1uF caps at the pins for the OPA633. The first step I did was increase the those caps to 10uF, however the chip showed now change. At this point, I am not sure how to proceed.

Any input is greatly appreciated.

Thank you

  • 0
    TI__Genius 9810 points

    Hi Dan,

    Could you confirm the iq of the device when just powered on is in the expected range? That is definitely something that should not be happening. Ensuring the device is powered on appropriately is the first step. Could you also remove any load at the output just to isolate the buffer stage. Could you also confirm the BW pin is pulled to Vs-? I was hoping you could maybe send exactly what you are seeing, and the board being used.

    Best Regards,

    Ignacio

  • 0
    Prodigy 10 points

    Hi Ignacio,

    Thanks for the quick response. I am happy to share the schematic for the adapter board with the BUF634, but this chat is not allowing me to insert a .pdf or snippet (png).

    Addressing your questions:

    I was able to measure the iq for the board out of circuit (no input/output). Applying +/-12V to the rails, the dual supply showed ~7mA for +12V and ~6mA for -12V; so both are below the typical 8.5mA shown in the datasheet.

    The BW pin has a 10ohm resistor in series with Vs- which, according to the datasheet, allows for the max bandwidth. Am I misunderstanding something in section 8.4.1?

    Looking forward to your response.

    Thank you

  • 0 in reply to Dan Rebello
    Prodigy 10 points

    Here is the schematic of the board used to measure iq

    J1-1 = V+ = +12V

    J2-5 = V- = -12V

  • 0 in reply to Dan Rebello
    Prodigy 10 points

    Here is the legacy design the BUF634 (A1) is being substituted in lieu of OPA633. *Note pin numbering below represents OPA633 PDIP (legacy) mapping; use the previous schematic to map between PDIP and SOIC.

  • 0 in reply to Dan Rebello
    TI__Genius 9810 points

    Hi Dan,

    Thank you for sharing the schematic. Could you put say a 1V dc signal at the input just so the input is not floating and confirm the output is around 1V? You are correct about the BW pin. Just to simplify the circuit could you directly connect the VS- to the BW pin, this should result in an Iq of 8.5mA and ensure the device is in wide bandwidth mode. The 10 ohms should not make a huge difference but shorting BW into Vs- should result in the Iq we are looking for. These two steps are to ensure the device is ultimately setup appropriately and the device is not damaged.

    Best Regards,

    Ignacio

  • 0 in reply to Ignacio Vazquez Lam1
    Prodigy 10 points

    Hi Ignacio,

    Using +/-12Vs, with 10ohm between BW and VS-, Vo = 1.033VDC when Vi = 0.975VDC.

    After shorting BW to VS-, Vo = 1.033VDC when Vi = 0.991VDC.

    Do these values seem valid? I was expecting a gain =<1?

    The output is nearly instant when tested "out of circuit" as shown in the first figure I sent. What would cause a chip to delay its output if both Vs rails are available?

  • 0 in reply to Dan Rebello
    TI__Genius 9810 points

    Hi Dan,

    The difference between the input and output is well within the expected range as this device has a max Vos of 65mV. As far as the delay, assuming the device is not current limited and the device is powered on appropriate, it is not normal behavior as you can see when you test the device directly on the adapter board. Could you send a scope shot of both the input and output when the device is connected to the circuit?

    Best Regards,

    Ignacio