OPA333 open loop gain

Thiago,

What you are missing in your consideration is the fact that the open-loop gain (AOL) decreases with frequency at -20dB/decade and since 20*log(1)=0 at the unity-gain frequency, AOL=0dB at f=350kHz. 

Therefore, AOL PDS spec of 130dB (3,160,000) refers to DC AOL and to find out where AOL will flatten out to -3dB DC value you need to make following calculations: DC_AOL = Unity-Gain_Bandwidth/DC_AOL = 350kHz/3,160,000=~0.1Hz

Thus to see DC AOL, you need to look at AOL curve below 0.1Hz - see AOL simulation below.

The OPA227 specs an AVOL = 160dB and have a full curve: 0.01Hz to 10MHz,

I suspect the difficulties are with the measurement equipment. Depending on the test circuit, I imagine the error voltage being measured could not be distinguished from the system noise.  

Regardless it would be nice to see consistency with the datasheets. Perhaps real world measurements backed up with silicon simulations at the transistor level to provide a full curve rather than leaving it up to the customer to calculate an expected response.

-Ken

Hi Marek-san,

Sorry let me ask you an additional basic question about "Phase characteristic".
The phase is started from +180deg, not 0deg.
I do not understand the reason why.
Would you tell me?

Best Regards,

Takumi,

The AOL graph shown above, depicts Phase Margin and NOT Phase Shift. The relationship between the two terms is:

Phase Margin =180 deg - Phase Shift 

Marek-san,

Thank you very much for your prompt response, I was surprised..

By the way, the graph means "phase margin", right?
I understood.
But sorry to ask you basic question, I suppose that the phase charcteristics usually means "Phase shift"...
Why do you plot the phase margin?
Of course, that is very useful for us to know the stability.

Regards,

Takumi,

Stability is the primary reason to show phase margin instead of phase shift and it’s done to emphasis how much phase may additionally shift before the circuit becomes unstable. Good rule of thumb is to design the circuit with the minimum 45 deg phase margin so when process variation results in a decrease of phase by up to 20 degrees, the circuit remains stable.

Marek-san,

Thank you for your reply!

I understood.

Regards,