At the risk of asking a Really Stupid Question (TM) :
One reason for using CMOS / JFET amplifiers is the very low input bias current - they can work well when you need to present a high input impedance to the signal source, but there appears to be a paradox : The Absolute Maximum Input Voltage is listed as supply plus or minus 0.5 volts. High impedance precludes the use of Schottky diodes for clamping to ensure that the maximum input voltages are not exceeded - the reverse leakage current of a Schottky will induce a significant voltage drop across a high input impedance, generating errors. The temperature dependency of the reverse leakage is cruel - whilst it may be almost acceptable at 25 degrees, it certainly is not at 105 degrees.
I saw a glimmer of hope in the datasheet's Note 2 on the Absolute Maximum Input Voltage : "Input pins are diode-clamped to the power supply rails. Input signals that can swing more than 0.5V beyond the rails must be current limited to 10mA". This *suggests* that the rating is stated not because there will be gate oxide damage by exceeding the rails, or any sort of latch-up, but rather that the issue is with the power dissipation in these diodes. If that is true, then the use of a high input impedance may in and of itself be adequate protection (although that is a little bit of a stretch of reasoning), but at worst one could add external low leakage silicon clamping diodes and not necessarily cause damage when the signal source exceeds the Maximum Voltage, since the diodes will limit the input pins to sensible, slightly-beyond-the-rails, voltages and the high impedance means that only tiny amounts of current are possible.
My question is whether this interpretation of the Absolute Maximum Voltage data is correct, and that the limiting element is the thermal limit of the input protection diodes, not a gate oxide or latch-up issue ?
Many thanks,
Pat.
