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Original question:
Hi,
one of my customer is testing TLV07 to measure the DC bus current in the boost stage of the solar inverter system.
The schematic is as below. Ipv1 is connected to TL074. TL074 forms a voltage follower, and the TL074's output is connected to the ADC pin of C2000.
It can work well during normal temperature.
But at 70-80C, Ipv1 will be -12V, TLV07 pin 2 voltage is 0V, pin 3 voltage is -10V.
At this time the boost will be turned down and their should be no current flowing through the shunt resistor RP104.
After cooling down the board, this phenomenon still exists.
After power cycle, the phenomenon disappear.
The failure rate is 4.1%.
Could you please provide any idea?
The main boost power stage is shown below, RP104 is shown there, solar-1 is connected to GND through 0 ohm resistor. Both Solar-1 and GND have large copper poured on the PCB on the same layer.
So I guess there should be no big inductance.
And this phenomenon could not disappear after power cycle.
OP07 from ADI with exactly the same circuit passed the aging test.
Howard,
Your customer's circuit should work just fine - see below.
However, your description of the failure, "at 70-80C, Ipv1 will be -12V, TLV07 pin 2 voltage is 0V, pin 3 voltage is -10V" does NOT seem possible since there are internal protection diodes, DOV1 and DOV2, between the input terminals that should keep pin 2 and 3 to be within a diode drop from each other - see below.
Having said that, your customer's problem seems like latchup condition or damaged device - does the part ever recover or not?
If it does not recover, this seems like an overvoltage related damage and customer must add extral EOS protection circuitry as shown below.
Schottky diodes, SD1 and SD2, protect the part from overvoltage on the positve input (for possible voltage spike on SOLAR-0) while transient voltage supressors, TV1 and TV2, prevent the damage due to excessive voltage on the supply pins that can be caused by spike on supplies and input voltage dragging the supply above absolute maximum rated voltage (e.g. LDO cannot sink current) or delay in power-up sequence between supplies (one supply is on while other one floats for few milliseconds). If the customer drives inductive loads with a possible inductive kickbacks, they must also add SD3 and SD4 together with Rout current limiting resistor to prevent the damage to output stage - see below.
I have also attached in this post a short presentation with more ESD/EOS protection details.
Losing one of the supplies (one supply floats) may lead to a latchup condition if there are no TVS's on supply pins to provide the path for the quiescent current to flow from a positive to negative supply.
There are back-to-back input protection diodes between the input terminals of TLV07 - see below.
The easiest way to measure the diode voltage drop in TLV07 is to pull the inputs apart with a voltage source, Vbat, and the internal 2.5k input resistors, R1 and R2, will limit the current to Iin=Vbat/5k - see below. This way you may limit the current to 10mA or less by appropriately choosing Vbat supply - no need to power TLV07 supplies. Under latched conditions, there may be another parasitic diode conducting the current and causing the problem your customer sees. For that reason, they should add overvoltage protection I discussed in my previous post to prevent this condition from occuring.
Hi Howard,
you cannot directly measure the protection diodes between pin2 and pin3 because there are internal 2k5 resistors in series with the protection diodes:
Kai
