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THS3217: expected -3db bandwidth is not getting.

Part Number: THS3217
Other Parts Discussed in Thread: THS3215

Hi Team,

We have designed a DAC circuit with using THS3217 part. Our design requirement as below,

  • Bandwidth (-3dB) at least 10MHz
  • Support output range +-5V
  • Output drive current >=25mA
  • Flatness> less than 0.5dB

But as per the below simulation model, we have getting very large -3db gain/frequency bandwidth (836Mhz) and also Bandwidth Flatness is more than 2dB.

Could you please suggest how to adjust output -3db bandwidth and  improve the bandwidth flatness.

We have 

DAC_THS3217.TSC

  • Hey Pradeep, 

    Thanks for the TINA file - the THS3217 is working as it should,

    1. You don't show a load past that 200ohm series out, probably should

    2. You don't need the 3V centertap on the input secondary - the balun will block the Vcm at the DAC and grounding that centertap will work a bit better - what you have will work also given the good CMRR of the input D2S stage. 

    3. If you need lower speed, 

    why not use the pin compatible lower power THS3215

    Increasing the output OPS feedback R will bandlimit directly at the cost of noise, here is an example, going to the THS3215 with 1kohm Rf and adding a 200ohm load gives a much lower BW of 280MHz. If you need much much lower maybe a passive RLC filter from the D2S output to the external OPS input might be the way to go, 

  • Hello Pradeep,

    I agree with Michael's comments, the model is working correctly in the sim you provided. 

    • Since you mention a 25mA output drive, I'm assuming the series 200-ohm you included is actually your load? If that is the case, both figure 40 & sims indicate you need a supplies of at least +/- 6.8V. 
    • If you don't plan on using pin VO1, datasheet recommends a 200-ohm load. "Lighter loading on the VO1 pin (versus the 100 Ω used to characterize the D2S only) results in increased frequency response peaking. Heavier loading degrades the D2S distortion performance."
    • I've included a sim of figure 100 which uses a 55-MHz RLC filter between the D2S & OPS stages.

    DAC_THS3217_Fig100.TSC

    Best,

    Hasan Babiker

  • Hi Hasan,

    Thanks for the feedbacks.

    One point our schematic is finalized and we can not add any extra components now. Only values we can change in existing design.

    Please let us know how we can achieve 25mA output current and 5Vpp and limited bandwidth by changing the component value/external LC filter.

  • Hello Pradeep,

    1. For lower feedback without filtering, take a look at Michael's suggestion of increasing the gain resistors.

    2. For 25mA output drive capability, you will just need to increase supplies to +/- 6.8V at the very least. I would recommend going higher to give some more headroom.

    Best,

    Hasan Babiker