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Original question:

TLV320AIC3120: Inquiry about MCLK

TLV320AIC3120: Is it correct to set this up? (use MCLK = 12.288 Mhz, ADC/DAC = 12 kHz)

Byoungjin Kim
Prodigy 40 points
Part Number: TLV320AIC3120
Other Parts Discussed in Thread: TLV320AIC3111, TLV320AIC3100

I am trying to set it up like this.
External input operates as I2S stream in FPGA.
MCLK=12.288Mhz, ADC/DAC=12khz

1) not to use PLL. Then, can I ignore the PLL constraint?

Can I use the settings below?

NADC : 1 / MADC : 4 / AOSR : 256 / ADC_fs : 12 khz

NDAC : 1 / MDAC : 4 / AOSR : 256 / DAC_fs : 12 khz

2) AOSR : 256, is it possible?

2.8Mhz <= AOSR x ADC_fs <= 6.2Mhz

Therefore, the AOSR should be 256.

3)  I want to use PRB_R4, R5, R6. Doesn't AOSR have to be 128? Can I use 256?

4) PRB_R25, P5 with DRC function will be used.
Can I use the settings above?

The FPGA's IP is configured for I2S communication at 256 times Fs.

So it would be nice to operate with the set clock. Is it possible to use it with the above setting?

If there are other better settings, please correct me.

  • 0
    TI__Genius 16905 points

    Hello Byoungjin,

    Thanks for reaching out. These are good questions. 

    Byoungjin Kim said:
    I am trying to set it up like this.
    External input operates as I2S stream in FPGA.
    MCLK=12.288Mhz, ADC/DAC=12khz

    I understand the CODEC is getting its I2S clocks (BCLK and WCLK) externally. Is this correct? If it is correct then the CODEC is a slave to the FPGA's (I2S) bus, and the Clock tree can be ignored all together. 

    However, if the CODEC is the Master then it is using the PLL to generate the I2S clocks for the FPGA. Based on a previous post ((55) TLV320AIC3100: AOSR setting - Audio forum - Audio - TI E2E support forums), it looks like an AOSR for 256 is only supported for the devices in the AIC31xx that have a miniDSP.

    I would ignore the constraint of 2.8Mhz <= AOSR x ADC_fs <= 6.2Mhz and follow the Required AOSR value 128 or 64 as listed in the datasheet. (Similar advise given in this post: (55) TLV320AIC3120: How do I set AOSR for 8 kHz sampling rate? - Audio forum - Audio - TI E2E support forums) 

    Please let me know if you need clarification on any of the points. 

    Best,
    Andrew

  • 0 in reply to Andrew Jackiw
    Prodigy 40 points

    thank you for the reply. 

    I don't understand something, ask again.

    Yes. A codec always works as a slave. The master of I2S is FPGA.

    I have already tested in different codecs via I2S, using an FPGA.

    I am going to use the TLV320AIC3120 for product development.

    This is to use the various functions of TLV320AIC3120.

    Functions of MIC input, AGC, Filter, Analog Volume control, PGA, DRC, and Speaker out are required.

    ADC Processing Block: PRB_R6 (Resource class 4, MADC x AOSR / 32 >= RC)

    DAC Processing Block : PRB_P25 or P5 (Resource class 12 or 6, MDAC x DOSR / 32 >= RC)

    The datasheet for the TLV320AIC3120 says that in some places it can go up to 128 AOSR, and in others it can go up to 256. Confusing.

    Also, the requirements of PRB_R6 are AOSR 128, 64.

    Does it work normally in AOSR 256?

    I have code that works like this. (applied other type codec)

    Fs = 12kHz

    MCLK = 3.072Mhz (12khz * 256)

    Bits = 24 bits

    However, to use the TLV320AIC3120,

    Under the condition that PLL is not used, (ignore condition 2.8Mhz <= AOSR x ADC_fs <= 6.2Mhz)

    MCLK = 3.072 Mhz

    NADC/NDAC = 1

    MADC/MDAC = 2

    AOSR/DOSR = 128

    --> Therefore, ADC_fs / DAC_fs = 12 khz

    Is it possible to use like this?

    However, to use the PRB block, to satisfy the Resource class, to satisfy MADC (MDAC) x AOSR (DOSR) / 32 > RC,

    MCLK = 12.288Mhz

    MADC/MDAC = 8

    AOSR/DOSR = 128

    With this configuration, does it work right?

    In summary, (same conditions for DAC)

    1) 2.8 MHz < AOSR × ADC_fS < 6.2 MHz => Can I ignore it?

    2) MADC × AOSR / 32 ≥ RC => must be met?

  • +1 in reply to Byoungjin Kim
    TI__Genius 16905 points

    Hi Byoungjin, 

    I apologize for the confusion. 

    Byoungjin Kim said:
    Yes. A codec always works as a slave. The master of I2S is FPGA.

    Andrew Jackiw said:
    If it is correct then the CODEC is a slave to the FPGA's (I2S) bus, and the Clock tree can be ignored all together. 

    Sorry for the misleading line here. The PLL portion of the CODEC Clock Tree (figure 7-33) can be ignored/bypassed since it is used to generate I2S clocks when the device is in master mode.

    When in slave mode, the rest of the Clock Tree is still needed generate the internal clocks for the ADC and DAC operation. 

    1) 2.8 MHz < AOSR × ADC_fS < 6.2 MHz => Can I ignore it?

    Yes, you can ignore this condition. However, you must use an AOSR of 128 or 64. 

    "The TLV320AIC3120 is a variant of other TLV320AIC31xx devices. AIC3120 is limited to simple Audio processing blocks, and others (like the TLV320AIC3111) have a fully programmable Mini-DSP.

    With the variants that only use processing blocks, the devices are limited to 3 decimation filters that support specific AOSR values. Filter A supports the highest AOSR rate which is 128. For the TLV320AIC3120, 128 is the highest supported AOSR." 

    (from TLV320AIC3100: AOSR setting - Audio forum)

    2) MADC × AOSR / 32 ≥ RC => must be met?

    Yes, this condition must still be met.

    Byoungjin Kim said:

    However, to use the PRB block, to satisfy the Resource class, to satisfy MADC (MDAC) x AOSR (DOSR) / 32 > RC,

    MCLK = 12.288Mhz

    MADC/MDAC = 8

    AOSR/DOSR = 128

    With this configuration, does it work right?

    Yes, I this configuration should work.

    Let me know if more clarification is needed. 

    Best,
    Andrew

  • 0 in reply to Andrew Jackiw
    Prodigy 40 points

    Thank you for answer.

    However, there remains an additional part that I do not understand.

    The datasheet 7.3.8 states that the AIC3120 is fully programmable.

    I'm not going to use programming, but you say that the AIC3120 has just a simple audio processing filter.

    Which one is true?

    It's confusing, but to sum it up

    If PRB_R6 is used, AOSR 128 or 64 must be used. Are you saying this? Is it right?

    Are you saying that 256 exists for a different purpose (programmable dsp)?

    <TLV320AIC3100 datasheet>

    <TLV320AIC3120 datasheet>

    -----------------------

    And Page1 / Register 7 is not listed in the datasheet.

    Is this post below correct?

    https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1118314/tlv320aic3120-register-of-pga-setting-page1-register47?tisearch=e2e-sitesearch&keymatch=TLV320AIC3120%252525252520register#

    I think, there is some typo in data sheet.

    I am so confused.

  • +1 in reply to Byoungjin Kim
    TI__Genius 16905 points

    Hello Byoungjin,

    These CODECs can get very complicated quickly. Thanks for staying on the thread and asking good questions. The above summary is correct. 

    If PRB_R6 is used, AOSR 128 or 64 must be used. Are you saying this? Is it right?

    • Yes, this is correct.

    Are you saying that 256 exists for a different purpose (programmable dsp)?

    • Yes, the fully range of the AOSR (1-256) is available for the miniDSP.
    • When using a processing block (like PRB_6), the miniDSP is disabled. 

    The AIC3120 offers two paths for signal processing, the miniDSP or the processing blocks.

    1. The processing blocks
      1. The Processing Blocks offer a predefined set of features use a fixed AOSR.
      2. The table you shared from the <TLV320AIC3100 datasheet> can be used as a reference here. 
    2. The miniDSP
      1. The miniDSP engine offers much more flexibility in terms of the AOSR programming. 
      2. Essentially all the equations from earlier in the post are to make sure that the selected AOSR is correct for the miniDSP. If the processing blocks are used then please follow the AOSR and rates listed in the tables.  TLV320AIC3100 is a good part to reference when miniDSP is not used. 
      3. The table you shared from the <TLV320AIC3120 datasheet> can be used as a reference here. 

    As you have noticed, a lot of the AIC31xx datasheets have sections and tables that are the same or slightly different since each device in the family is based on the same technology. 

    Byoungjin Kim said:

    Is this post below correct?

    https://e2e.ti.com/support/audio-group/audio/f/audio-forum/1118314/tlv320aic3120-register-of-pga-setting-page1-register47?tisearch=e2e-sitesearch&keymatch=TLV320AIC3120%252525252520register#

    I think, there is some typo in data sheet.

    Yes, this post if correct. Although, it is confusing. I don't think this case is a typo. Since the table from <TLV320AIC3120 datasheet> is still correct for the miniDSP.

    Did this help clear things up? 

    Best,
    Andrew

  • 0 in reply to Andrew Jackiw
    Prodigy 40 points

    Thank you Andrew.

    I understand what is involved.