TAS5755M: SSTIMER should be disabled in case 2.1ch?

KANJI SHIBATANI

Mastermind 6205 points

Part Number: TAS5755M

Hello

My customer intend to use 2.1ch for TAS5755M .

I had tested TAS5755MEVM by myself.

SSTIMER pin is as default ( 2.2nF is between SS timer and gnd)

In case 0x1A register is 1Ah ( SSTIMER enabled), POP is seen, 0x1A is 88h, no pop.seen.

( see attached )

Is my test correct?

SSTIMER function should be disabled in case 2.1ch? ( Is customer should so, pop in case 2.1ch is same level

as 2ch BTL?)

Please advise

Best Regards

TAS5755_SE_POP_EVM testing.pptx

over 6 years ago

0 Shawn Zheng over 6 years ago

TI__Mastermind 24835 points

Hi Kanji-san,
The TAS5755M uses a special mid-Z ramp sequence to reduce click and pop in SE-mode and 2.1-mode operation. To enable the mid-Z ramp, register 0x05 bit D7 must be set to 1. To enable 2.1 mode, register 0x05 bit D2 must be set to 1. The SSTIMER pin must be left floating in this mode. So please remove the 2.2nF capacitor on SSTIMTER pin.
Best regards,
Shawn Zheng