Hi Adam Siismets
Previous ticket has been locked and I am not able to udpate status. So I open new ticket with the same question.
At Previous ticket, You gave some idea as below.
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Can you confirm that you waited for the device to stabilize in the error state before pulling PDN low for 2ms? Again, it would be helpful to see a plot of VDD and PDN vs time to make sure the ramp is monotonic and that PDN doesn't ramp up too quickly.
As for the N divider problem, could you route PLL RDIV/2 and PLL NDIV/2 to the Status0 and Status1 pins and send plots for the N divider at 64 and 66? This will help verify that the PLL is working properly. I will do the same measurements so that we can compare.
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Regarding PDN and VDD, I checked the plot of both VDD and PDN. PDN was plot in yellow. Now customer check VDD Plot in order to make Supply rail ramped in monotonic manner.
However, We'd like you to cofirm if VDD ramp can cause reported problem.
When issue was reproduced
1) R50 (Input select): 0x53
select PRI (PRI/Sec : differential input mode)
2) R29 (control over input):0x0f
3) R13(INT Status): 0x00
-> there was no interrupt for loss of lock, loss of input
4) status pin
-. status pin #1: 1
-. status pin#2: : 0
