I am designing a system to generate MCLK for audio converters from external word clock (LRCLK). Your application note looks perfect for what I need but I need to support many word clock rates from 44.1k to 192k. I see in the application note that it is suggested to use multiple CDCE913's in order to use multiple input rates, as I need to support 6 different input rates this becomes costly for the application. Couldn't I program the CDCE913 with different divider ratios to place the VCO and phase detector in the right pulling ranges? Worst case I could see needing 2x CDCE913's to support 44.1k and 48k and their multiples, but the fractional divisions seem adequate.
Please let me know if this would lead to bad jitter performance or if I'm missing something.