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LMH1983: Lock time to Vsync

Hirokazu Takahashi
Expert 8420 points
Part Number: LMH1983

Hello Support team,

After the process of Power on -> clock input to Vsync and Hsync -> I2C confutation
How long time is it required to make the output clocks (148.35MHz NT, 148.5MHz PAL) follow the input signals?
How long time is it required to make the output clocks lock to Vsync?

If you have min/typ/max value spec, please let me know.
If you don't have any spec, please share the actual measurement value.

Output clock : CLKOUT2
Register configuration : below

LMH1983 register.xlsx
Best Regards,
Hirokazu Takahashi

  • 0
    TI__Guru* 86220 points

    Hi Takahashi-san,

    We don't have this data in the datasheet. This input-to-output time will depend mainly on the lock time of PLL1. 

    The loop filter in the EVM has a loop bandwidth of 3Hz. As such, the lock time of PLL1 will be roughly around 1.3s (if cycle-slipping does not happen). You may assume the overall input-to-output time is around 2s.

  • 0 in reply to Noel Fung
    TI__Expert 8420 points

    Hello Fung-san

    Thanks for your support.

    Does "Input-to-output time" mean the time range when PLL1 can synchronize CLK1 Out with V sync or H sync? 

    The customer uses mainly 148MHz clock output with PLL2 and 3.

    Does "Input-to-output time" include the lock up time of PLL2 and 3? Or can we neglect the lock up time at PLL2 and 3?

    Since LMH1983 uses external component's  for VCXO and Loop filter, I guess the lock time will have the large deviation depended on them.

    My understanding is correct?

    Do you have any formulas to calculating the lock up time of PLL1?

    Best Regards,

    Hirokazu Takahashi

  • 0 in reply to Hirokazu Takahashi
    TI__Guru* 86220 points

    Hi Takahashi-san,

    Correct, input-2-output time meant the time taken for the device to sync the input signals and generate valid output clocks. PLL1 lock time is in the range of millisecond to second while the lock time of PLL2/3 is in the range of µs. The overall lock time is therefore dominated by PLL1. 

    The lock time of a PLL is approximately equal to 4/loop bandwidth. For example, if the loop bandwidth is 1kHz, then the lock time is approx. 4ms. However, if the loop bandwidth is much smaller than the fpd, cycle slipping may happen. Then in this case, the lock time will be much longer. The following has additional information on cycle slipping. https://www.ti.com/lit/pdf/snap002.