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LMX2492EVM: Losing lock with 200 MHz PFD

KJ
Prodigy 60 points
Part Number: LMX2492EVM
Hi,
I'm using LMX2492EVM to generate X-band signal. To minimize phase noise and more importantly spurs, I would like to have maximum PFD (200 MHz) and minimum loop bandwidth. I've simulated and measured several filters starting from ~90 kHz to ~380 kHz LBW (sim. for latter case attached below):
 
 
Overall performance is quite good and with agreement with simulation, but there is a problem with jumping >40 MHz between lower to higher frequency at PFD 200 MHz, for example (9800 MHz -> 9850 MHz), in which case PLL loses lock and is stuck at ~9600 MHz and only becomes responsive after changing PFD to 100 MHz (disabling doubler). There is no problem with jumping from higher to lower frequencies at PFD 200 MHz, and also no problem at all with 100 MHz PFD (even though fixed filter elements result in lower loop bandwidth).
Changing different CSR options did not help.
So my questions are: what could cause such behavior at high PFDs (i.e. completely losing lock)?
Is there any way to achieve low loop bandwidth at high PFDs?
Best regards,
Konrad
  • +1
    TI__Mastermind 27661 points

    Konrad,

    In this case, it is not obvious what the cause is, but here's two experiments that likely will be able to direct us towards the root cause.

    1.  Theory #1:  Cycle Slipping

    -  CSR doesn't help, so I don't think cycle slipping is the issue.  But you might want to also try to change the charge pump current to change the loop badnwidth without changing the phase detector frequency and not N divider or phase detector frequency.   If you have it maxed out, try reducing this current and seeing if it agitates the problem.  I expect it not to, but if it does, then reconsider cycle slipping.

    2.  Theory #2:  N Divider

    If there is some issue related to the N divider, try reducing the modulator order or the PFD_DLY settings to see if it has an impact.

    3.  Theory #3:  Misprogramming

    Just want to make sure that there is no programming issues causing this.

    4.  Theory #4:  Input reference

    The input doubler works by clocking on both the rising and falling edges of OSCIN.  If there is an issue with OSCin, such as it NOT having 50% duty cycle, then this would cause very high jitter, maybe enought to cause locking issues.  To test this theory, try driving with a signal generator. 

    Also, one diagnostic to try would be to try direct 200 MHz from a signal generator without the doubler to help discren if the issue is related to the N divider or the doubler.

    Regards,
    Dean

  • 0 in reply to Dean Banerjee
    Prodigy 60 points

    Hi Dean,

    narrowing down from the points that you've mentioned, I've focused my attention back to cycle slipping, which in fact turned out to be the problem.
    In my previous measurements FL_TOC value was set too low.

    Eventually for (FL_TOC = 200 and FL_CSR = 2x) I was able to jump in practically entire VCO range (9.4~10 GHz) with no lock problems.

    Thanks for help,
    Konrad