LMK05028: Several questions

Hirotaka Matsumoto

Part Number: LMK05028
Other Parts Discussed in Thread: LMK05318

Hi all

Would you mind if we ask LMK05028?

<Question1>
How much of value should we set these value?
-Frequency Detect Threshold
-DPLL Frequency Lock Detectors
-DPLL Phase Lock Detectors

-XO input tolerance : ±25ppm
-Reference input tolerance : ±30ppm

<Question2>
Is it to possible to operate following reset in a row?
Register R12 : Software Reset ALL functions
Register R676 : Software Reset Output Channels
Register R677 : Software Reset PLL2 , Software Reset PLL1
As the background of this question, the customer operates "Register R12 : Software Reset ALL functions" in a row", the output clock was not unstable.

Kind regards,

Hirotaka Matsumoto

over 2 years ago

0 Kia Rahbar over 2 years ago

TI__Expert 8585 points

Hello Hirotaka,

1. The DPLL lock detectors will vary based on your required configuration. If you press the Run Script button shown below, the GUI will automatically calculate the optimal settings for your configuration.

2. Yes, it is possible. Please re-write all the registers by pressing the Write All Registers button and then try performing a Soft-reset Chip.

Regards,

Kia Rahbar

0 Hirotaka Matsumoto over 2 years ago in reply to Kia Rahbar

Guru 27565 points

Kia san

Thank you for your reply.

The DPLL lock detectors will vary based on your required configuration.
If you press the Run Script button shown below, the GUI will automatically calculate the optimal settings for your configuration.
->We recognize that the GUI will automatically calculate the optimal settings for your configuration using TICSPRO's Run Script.
As our request, in spite of XO input tolerance or Reference input tolerance, should we use calculated number?
And does average number mean the same as following URL?
https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1060029/ticspro-sw-ticspro-in-case-of-using-lmk05318

Yes, it is possible. Please re-write all the registers by pressing the Write All Registers button and then try performing a Soft-reset Chip.
->As the background of our question, after R12's reset, the device starts to operate several sequence.
So, when R12's reset operates repeatedly, we suspect the device mis-operates.
Could you give us advice?

Kind regards,

Hirotaka Matsumoto

0 Kia Rahbar over 2 years ago in reply to Hirotaka Matsumoto

TI__Expert 8585 points

Hello Hirotaka,

1. If you have performed a run script, then the current DPLL Frequency lock and DPLL phase lock do not need to be change and will work for your XO and reference tolerance. The average numbers shown in the other post are for the LMK05318, not the LMK05028.

2. Can you please provide the sequence that occurs?

Regards,

Kia Rahbar

0 Hirotaka Matsumoto over 2 years ago in reply to Kia Rahbar

Guru 27565 points

Kia san

Thank you for your reply!

1. If you have performed a run script, then the current DPLL Frequency lock and DPLL phase lock do not need to be change and will work for your XO and reference tolerance. The average numbers shown in the other post are for the LMK05318, not the LMK05028.
->We would like to confirm one point. On your description "DPLL Frequency lock and DPLL phase lock do not need to be change ",
does it mean that it doesn't need to consider XO input tolerance and Referece input tolerance?
As our assumption,
Example) At setting of DPLL Frequency Lock Detect
-XO input tolerance : ±25ppm
-Reference input tolerance : ±30ppm
->In this case, we think that it should be set the value more than each ppms like as Lock ppm = 200ppm and Unlock ppm = 300ppm.

2. Can you please provide the sequence that occurs?
->As our assumption, R12's reset sequence is followings;
1 : during reset sequence
0 : complete of reset sequence
If when R12's reset operates repeatedly, should we confirm 0(complete of reset sequence)? 0->1->0
We heard from the customer ;
"to try performing a Soft-reset Chip on TICSPRO in a row, the output clock was not unstable sometimes."

And then, Avg number which was generated by TICSPRO is recommended also?
What is "Avg number" used for?

Kind regards,

Hirotaka Matsumoto

+1 Kia Rahbar over 2 years ago in reply to Hirotaka Matsumoto

TI__Expert 8585 points

Hello Hirotaka,

1. Correct, the DPLL Frequency Lock and DPLL Phase Lock Detectors are not dependent on the XO input tolerance and the reference input tolerance. The run script will calculate the optimal settings for your lock settings based off of your XO frequency, reference input frequency, DPLL LBW, and TDC rate.

The XO input tolerance and reference input tolerance only affect the Frequency Detect Threshold.

The minimum valid threshold should be max XO frequency error + max PRIREF / SECREF frequency error + accuracy in ppm. The minimum invalid threshold should be valid threshold + accuracy in ppm.

Since your XO has 25 ppm error and your reference has 30 ppm error, please set valid to 65, unlock to 75, average to 10.

2. Yes, please confirm the reset is low (0) before performing another reset. Also, it is not clear to me why you need to perform multiple resets in a row. One reset should be enough.

3. Yes, the run script will update the average number to the recommended setting for your configuration.

For the frequency detect threshold, Avg will control the time it takes for the reference input to be detected as having a valid frequency.

For the DPLL Frequency Lock Detector, the Lock Avg sets the time it takes for the DPLL_LOFL to go low once a valid reference is inputted.

The Unlock Avg sets the time it takes for the DPLL_LOFL to go high once the valid reference no longer exists.

Regards,

Kia Rahbar

Clock & timing

Clock & timing forum

LMK05028: Several questions