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LMX2594: Oscin, RFout, Phase relation

remi sassella
Prodigy 40 points
Part Number: LMX2594

Hello,

First, I work with integer mode with LMX2594 and two external generators, both locked on 10Mhz lab reference.

Lab Gen1 =Fosc=128Mhz; FreqPFD=32 Mhz ; LMX2594 Fout = 7744Mhz

Lab Gen2 = 7744Mhz+128Mhz=7872Mhz

Un mix both previous signals with RF mixer: I keep de 128Mhz différence to oscilloscope

I look also the Gen1 signal to osciloscope

 Thus I can see the phase between both 128 Mhz signal with oscilloscope : No phase drift , I adjust the phase difference to 0° ( Lab Gen phase adjustment), all devices are phase locked, all is ok

 

I simulate the loose of Fosc signal, thus I switch RF on:off (front panel generator, or coax removed)

When Fosc is ‘’on’’, LMX2594 lock again. But… phase difference could be 0° or 180° : random

Could you provide more information about phase detector curve response? Is it 0-2PI or 0-4PI or.. ?

 

I don’t have the same behavior with other integer PLL system: phase is always the same.

See attached tcs file

Regards7744integermode.tcs

  • 0
    TI__Guru* 81750 points

    Hi Remi,

    Could you try again with fpd = 128MHz? You need to change FCAL_HPFD_ADJ accordingly to match the fpd. 

  • 0 in reply to Noel Fung
    Prodigy 40 points

    Hello Noel,

    Many thanks for your fast answer. You are right. If we suppress the R divider, it works : PFD  is synchronized with Fosc input. It works in integer mode : Fosc= 128 Mhz and Fout = 7680=60*128. I understand that R divider = 4 , at 32 Mhz output have the same output , even if Fosc 128Mhz phase change from 0 or 180°.

    It works also with mash modulator every time that Fout=N*Fosc. If N is integer, without integer mode, mash modulator don’t introduce phase offset.

    Now I need to understand why the mash modulator will introduce phase offset, randomly ( May be 2 or more typical value, when I turn on/off 128Mhz generator) for fractional case : Fosc=128Mhz, Fout =7744Mhz =60.5 * 128.

    Please look at my TCS file. Did you have any explanation ?

    Regards

    7744ref128fract.tcs

  • 0 in reply to remi sassella
    TI__Guru* 81750 points

    HI Remi,

    The "N-divider" is a counter, so it is never fractional. The way that we can archive a fractional number is by taking the average of several integer numbers. For example, 60.5 can be obtained by taking the average of N=60 and N=61. That is, at a particular fpd cycle, we use N=60. in the next fpd cycle, we use N=61. With a third order MASH, we will use 8 different N-divider values to get the average of 60.5. As a result, the phase between the VCO and the reference clock (since R=1) will not be consistent. 

    According to your configuration, it is classified as a Cat. 3 sync. That is, in order to phase align the output with the input clock, special operation is needed, please check section 7.3.11 of the datasheet for details. 

  • +1 in reply to Noel Fung
    Prodigy 40 points

    Hello Noel

    Many thank’s to confirming what I suspect. I know fractional principle and I build a discrete PLL with mash modulator in 2000. Our concern was the noise rejection, not the phase. Thus, I discover a new issue today.

    The 7.3.11 explain how to adjust phase. My issue is more: unpredictable relative phase when the reference returns. I will also read about sync vco feature. But if you read at  https://www.iram-institute.org/EN/noema-project.php?ContentID=9&rub=9&srub=0&ssrub=0&sssrub=0 you will understand than I need to synchronize 4*12 synthesizer..which is not obvious.  Today I plan to use 32 MHz reference, without fractional ratio, with or without mash modulator.

    Regards