LMK1D1208: Duty cycle

Hugh Yang

Part Number: LMK1D1208

Hi Teams，

Recently, I am working with my customer to qualify lmk1d1024/8.
1) Customer wanna use its IN1 multiples lvds signal from fpga. The f of input is 200kHz and the duty cycle is 0.2%. I am not sure if it’s proper. I have not seen any related descriptions in datasheet.

2) If it works, any limitations for Ton?

Thanks,

Br,

Hugh

over 2 years ago

0 Julian Hagedorn over 2 years ago

TI__Mastermind 20900 points

Hi Hugh,

that is not a problem. 0.2% of 200kHz result in a 10ns pulse.

Minimum ton (or min toff for very high duty cycle applications) for a pulse can be calculated with the max allowed frequency. For single ended inputs it is 250MHz or 4ns. For differential signals it is 2GHz or 500ps.

regards,

Julian

0 Hugh Yang over 2 years ago in reply to Julian Hagedorn

TI__Intellectual 820 points

HI Julian,

Thanks for you support.

And I am little confused with the 'ODC'. If the input duty cycle is 0.2%, will the output duty cycle in range [0.018%,0.022%] ?

Br,

Hugh

0 Julian Hagedorn over 2 years ago in reply to Hugh Yang

TI__Mastermind 20900 points

Hi Hugh,

The output duty cycle will vary a bit over frequency, temperature, process and supply voltage.

Even though we have not characterized this with a 0.2% duty cycle, the 10% variation should be correct. With a given frequency and supply voltage, the variation should be actually smaller than 10%.

regards,

Julian

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LMK1D1208: Duty cycle