CDCS502: SSC Triangular modulation

Andrea,

We have an application note https://www.ti.com/lit/an/scaa103/scaa103.pdf which goes into some detail about the SSC used in the CDCS502. I believe this is a frequency modulation scheme, imparting between 30kHz and 100kHz of modulation based on the VCO frequency of the internal PLL. While the exact implementation is a bit opaque to me, it seems like the modulation frequency is always related to the input frequency per the datasheet equations. For instance, with a 25-MHz crystal, and a 25-MHz output frequency, I would expect the modulation frequency to be 25 MHz / 708 = about 35.3 kHz; compare with 100-MHz output, where I would expect the modulation to be at 25 MHz / 620 = about 40.3 kHz. Amplitude in SSC would be given by the spread options, e.g. ±1% spread on a 25-MHz output would have an amplitude of ±250 kHz. Since the SSC implementation uses a PLL and VCO combination at higher frequency, I suspect there will always be some rational fractional relationship between the modulation phase and the input signal phase. I would also expect some kind of dithering strategy to try and avoid fractional spurs - but I have no idea what that would be, and our design documentation is somewhat lacking on this device 

Regards,

Derek Payne