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Original question:

question: 10MHz clock and interface recommendation

LMK1C1106: Non-clock application

Erik Anderson
Prodigy 30 points
Part Number: LMK1C1106
Other Parts Discussed in Thread: CDCLVC1106

Hi,

We intend to use LMK1C1106 to buffer a SPI clock that fans out at 50MHz to multiple ADCs.  However, we are also thinking to use it for the MOSI signal, which is not a clock.  Is this okay?  I don't think the device has an internal PLL, right?

Thank you,

Erik

  • 0
    TI__Mastermind 20900 points

    Hi Eric,

    that is possible with that device. LMK1C1106 does not have a PLL internal and can buffer data signals.

    Note that the LMK1C11xx family has a synchronous output enable that requires typ 2 (max 5) clock cycles to enable/disable. This is also needed after startup.

    If you can toggle the MOSI/CLK pins after power up a few times before communicating with SPI, then there is not problem. Otherwise you can use the pin2pin part CDCLVC1106 which has asynchronous enable/disable.

    regards,

    Julian

  • 0 in reply to Julian Hagedorn
    Prodigy 30 points

    Hmm, ok well we need 1.8V so we can't use the CDCLVC1106.  And seems strange that the it could be between 2 and 5 clock cycles - was hoping it would be more deterministic.  But I guess we could just write twice to the ADCs on power up, that will work.  If you have another part that async at 1.8V, let me know, thanks!

  • 0
    TI__Mastermind 29830 points

    Erik,

    There's three stages of flip-flops within the LMK1C1106, so the first three rising edges of MOSI after POR will be absorbed. After these flip-flop stages are initialized, the device should behave as a 1:1 buffer for CMOS signals. You can use LMK1C1106 for MOSI distribution, but you will need to somehow toggle MOSI pin to produce at least three rising edges before attempting real communication.

    Regards,

    Derek Payne

  • 0 in reply to Derek Payne
    Prodigy 30 points

    Thanks, all is clear now.  We will move forward with this device.  We'll put another FPGA state to initialize the flip flops.