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LMX2541: Default register settings at power up unclear

Markus Roggli
Prodigy 40 points
Part Number: LMX2541

We are using the LMX2541SQ3740E and discovered the following strange behavior:


At power up the state of the pin 20 (Ftest/LD) is not well defined. We have installed a 1k Ohm pull-up to 3.3V on this pin.
If not configured some devices show a high level others a low level on that pin.
After the configuration the MUX register (MUX[3:0] = 4), everything is fine.
Now my question, what is the power up state of the MUX[3:0] register, I do not find any information in the data sheet (SNOSB31J –JULY 2009–REVISED DECEMBER 2014). For some registers, the default state is mentioned in the data sheet.

Are all not mentioned registers set to zero at power-up? 
If, yes MUX[3:0] would be 0, which means "High Impedance", but then it should not be possible to have different power levels if the chip is not configured. It should always be a high level.

  • 0
    TI__Guru* 81710 points

    Hi Markus,

    After a reset (program R7), the registers will be reset to their silicon default value, which is not always =0. The silicon default value of MUX is 15 (0xE). Unfortunately I don't know what exactly is the status with this register value. If the external pull-up resistor can fix the output state at start-up, I think it is a good solution. 

  • 0 in reply to Noel Fung
    Prodigy 40 points

    Hi Noel

    Thank you for the information. How did you find out the default setting of the MUX register is 0xE?
    The data sheet states 0xE and 0XF are reserved. The pull-up did not solve my problem at power up. I guess we have to live with that. After the configuration of the chip all is ok.

  • 0 in reply to Markus Roggli
    TI__Guru* 81710 points

    Hi Markus,

    Internal document shown the silicon default value of MUX is 0xE. However, the document did not tell what does reserved mean. If the pull-up resistor cannot help, I don't have other suggestions.