Hello,
I would like to have our schematic reviewed.
The design includes LMK04828 to support ADC32J25IRGZT and Xilinx FPGA.
Thank you,
Andrew
Hi Andrew,
That's correct. Usually for the JESD204B complaint clocks, FPGA requires the low frequencies (FPGA REFCLK / CORECLK in few 100 MHz) and that should be able to generate using the LMK04828.
For the integer clocks out frequencies (SYSREF - 8MHz, DACCLKP/N - 160MHz, FPGACLKP/N - 160MHz and MGTREFCLK0P/N - 80/16/320MHz), LMK04828 internal VCO should be LCM of these frequencies and VCO can be selected 2.4GHz. To have better phase noise / jitter performance, phase detector frequency should be higher. Hence need to replace the existing 122.88MHz VCXO with the integer frequency VCXO, say 100MHz / 160MHz.
Attached is the TICS Pro config file FYR.
Regarding the LMK04828 schematic, please see the feedback below:
1. Should be follow the supply section guidelines from section 10.6 in datasheet and based on LMK04828EVM user's guide.
2. OSCin input requires the 100ohm differential termination for LVPECL input signal. Hence, can keep 100ohm before C183/C184 and insert same cap after R138/R141 to isolate the common mode voltage variation.
3. SYSREFout signals should be from the odd clocks out (SDCLKoutX).
4. If MGTREFCLK0P and FPGACLKP has the same frequency from DCLKou0 and SDCLKout1, then should be ok, otherwise change these clocks to different DCLKout.
5. For LVDS output, if the FPGA has internal 100ohm impedance, then need to provide the 560ohm otherwise keep 100ohm.
6. What are the clock frequency and output format for CLK_TX and CLK_RX? If both are same frequency, then its good else change to other DCLKout.
Thanks!
Regards,
Ajeet Pal
Hi Andrew,
Your frequency plan looks good and seems you are operating LMK04828 in dual PLL mode with on-board reference (CLKin1) or external reference from CLKin0 (J16). All input reference pins terminations are good.
With the 40MHz VCXO, you can keep the PLL2 phase detector frequency 80MHz using the doubler in path, which would help to improve the overall phase noise / jitter performance. In the PLLatinum Sim tool, you can import the VCXO data and can simulate alongwith to get the performance including VCXO.
I am not seeing the SYSREF output for FPGA. Usually for JESD204B complaint clocks, FPGA would also require the SYSREF input. Please ensure from FPGA side and include that too, if needed.
Thanks!
Regards,
Ajeet Pal
Hi Andrew,
TICS Pro config file looks good, except you can have sync enable to reset the clock dividers to have all outputs aligned/deterministic delay between them. The sync event can be occur once PLL2 locked (SYNC_PLL2_DLD --> 1), keep SYSREF_MUX in "normal sync" mode and SYNC_DISx/SYNC_DISSYSREF --> 0. Once, the divider are reset after locking the PLL2, change SYSREF_MUX in Continuous (Once the JESD link is establish, turnoff the SYSREF to avoid SYSREF spurs at DCLK) and SYNC_DISx/SYNC_DISSYSREF --> 1.
For the noise sensitive clocks, I would suggest to use those clocks from different clock group, which will have less crosstalk between clocks out (like you have ADC clocks from CLK group 1).
Thanks!
Regards,
Ajeet Pal
I have also noticed you have arrived at 2400 MHz VCO0 slightly different
N divider is set to 100
PLL1 phase detector frequency is 0.4 MHz
Hi Andrew,
For the FPGA clocks, I think all termination looks good and configured for LVDS output.
Regarding the ADC clock inputs, I believe you should be following/review from ADC side. That means, the LMK04828 should meet the ouptut swing and common mode voltage (for DC coupled).
ADC32J25EVM schematic:
Right now, you have configured SYSREF in AC coupled with LVDS but it may not support the amplitude requirements. I think, you should changed the output termination based on EVM schematic and go ahead if AC coupled or DC coupled SYSREF options.
Thanks!
Regards,
Ajeet Pal
