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LMX2492: Transient Response and in-band Noise

Hani Esmaeelzadeh
Prodigy 10 points
Part Number: LMX2492
Other Parts Discussed in Thread: LMX2594,

Hi,

We are considering LMX2492 for one of our projects. We have the following questions:

  1. Is there a time domain model to evaluate settling behavior?
    1. If fast lock & cycle-slipping reduction is not used (consider max Icp already used in design), is there any internal techniques used to improve settling behavior (especially cycle slipping) compared to a classic frac-N PLL (look at the plot below)?
  2.  We noticed that the in-band noise of LMX2492 (both flat and flicker) are a lot worse than some other TI PLLs (e.g., 9dB worse compared to LMX2594: -227 vs -236 & -120 vs -129)
    1. Is LMX2492 worse by design?
    2. What are the testing conditions under which the noise was characterized?
  3. The in-band noise of a PLL under FMCW modulation is elevated due to increased charge-pump activity compared to a static PLL in steady-state
    1. Is that considered in the flicker and flat noises reported in the datasheet?
      1. If yes, what FMCW conditions were assumed (chirp rate, etc)?
      2. If not, how much degradation should we expect when LMX2492 is under a certain modulation?
  1. For our project, we would need variation in both the integer as well as the fractional part of the feedback divider when PLL is under FMCW. For certain DSM implementations, we noticed that if the integer part varies, it causes freq humps in the frequency ramp profile which will lead to spurious radar output (look at the plot below).
    1. Are these humps expected in LMX2492?
    2. Any techniques used by design to mitigate this?

  • 0
    TI__Genius 12550 points

    Hi There,

    Our expert on PLL with chirp generation is OOO for couple of days and will be responding soon within this week.

    Hani Esmaeelzadeh said:
     We noticed that the in-band noise of LMX2492 (both flat and flicker) are a lot worse than some other TI PLLs (e.g., 9dB worse compared to LMX2594: -227 vs -236 & -120 vs -129)
    1. Is LMX2492 worse by design?
    2. What are the testing conditions under which the noise was characterized?

    Yes, both devices are designed for different applications, where LMX2492 is used external VCO whereas LMX2594 is integrated VCO and both have different noise profile.

    Thanks!

    Regards,
    Ajeet Pal

  • +1 in reply to Ajeet Pal
    TI__Guru* 85740 points

    Hi Hani,

    You can use PLL Sim to simulate frequency switching response. https://www.ti.com/tool/PLLATINUMSIM-SW. 

    LMX2492 is a PLL device, except for fast lock and cycle-slipping reduction, there is no other technique that a PLL can do to speed up frequency switching response. One thing we may try is use film capacitor in the loop filter. Film capacitor tends to have faster response speed than ceramic capacitor.

    PLL flicker noise and flat noise describe the noise characteristic of a PLL. Flicker noise does not depend on DSM but flat noise will get worst at fractional channels. Depending on the fraction configuration, in-band noise may vary a lot especially when doing FMCW modulation, fraction configuration is kept changing while the loop filter bandwidth is wide. I have seen 10dB increase in phase noise during ramping.

    Using LMX2492EVM, I do not see the humps when DSM integer change. First plot is Vtune vs time; second plot is freq vs time.

    This is div/2 output from the EVM, VCO frequency changes from 9600MHz to 10000MHz, with fpd=100MHz. 

    Frequency ramping setting:

    Ramp 0: 9600MHz --> 9600MHz in 10µs

    Ramp 1: 9600MHz --> 10000MHz in 40µs

    Ramp 2: 10000MHz --> 9600MHz in 5µs

    I see similar cycle-slipping-like ramp down response if do a DSM reset, instead of asking it to ramp down in 5µs in Ramp 2.

  • 0 in reply to Noel Fung
    Prodigy 10 points

    Hi Noel,

    Thank you so much for your reply.

    Regarding the in-band noise, aside from DSM, we observe increased charge-pump activity during FMCW (CP has a longer activation time in each period compared to steady-state) which is expected to increase both flicker and flat noise. It seems that PN1Hz=-227 and PN_1/f=-120 mentioned in the datasheet are measured when PLL is in steady-state and does not take into account the extra noise from when PLL is under modulation which seems to be significant.

  • 0 in reply to Hani Esmaeelzadeh
    TI__Guru* 85740 points

    Hi Hani,

    for sure FOM and 1/f noise is measured without modulation. Usually we will pick an integer channel to measure these figures. FOM and 1/f defines the noise characteristic of a PLL. For example, if you have two PLLs with different FOM, you can expect to get a better in-band noise with the PLL having better FOM. 

    During ramping, most of the time, we are working in fractional channels, the phase noise degradation you see is not due to FOM or 1/f noise degradation, it is due to the fractional spurs. For example, given fpd = 100MHz, phase noise will be the same when VCO = 3000MHz and 3001MHz when PLL_DEN = multiple of 1000 (e.g. 1000, 2000, ,..,etc). The difference between these two frequency output is, you will see discrete spurs at multiple of 500kHz offset (sub-fractional spur frequency). 

    Now, if the VCO frequency is 3000.01kHz, then we will see a lot of 5kHz spurs. Because of log scale, these spurs appear as continuous signal, making it look like phase noise is getting worst.

  • 0
    Prodigy 10 points

    Hi Noel,

    Thank you so much for the extra data.

    I have the following questions:

    1. What is the delay between the external trigger for chirp enable and the start of the chirp at the PLL output?

    2. What is the variation of the above delay?

    3. Can LMX2492 generate a synchronized chirp enable signal that can be used by other parts of the system (such as TXRX_enable, ADC_en, etc.)?

    4. Do you have any amplitude noise measurement?

    What is the absolute value of td1 and td2? what is the expected variation of these two delays? (we need a synchronized signal to the start of ramp for other parts of the system and it seems that flag0/1 does the job?)

    Thanks,

    Hani

  • 0 in reply to Hani Esmaeelzadeh
    TI__Guru* 85740 points

    Hi Hani,

    I can get you some bench data in next week. However, I won't be able to provide the variation. 

    No, we don't have amplitude noise data.

  • 0 in reply to Noel Fung
    Prodigy 10 points

    Thanks, Noel. Looking forward to getting the data.
    Could you also clarify what the following highlighted signals mean in the datasheet? We are trying to find an output signal from LMX2492 that is synchronized to the beginning of the chirp to trigger other parts of the system.

  • 0 in reply to Hani Esmaeelzadeh
    TI__Genius 11255 points

    Hi Hani,

    Noel is out of the office today and will hopefully be able to reply later this week.

    Best,

    Evan Su

  • 0 in reply to Evan Su
    TI__Guru* 85740 points

    Hi Hani,

    My scope cannot give me the resolution, looks like both delays are zero.

    You can setup a Flag output at the beginning of a ramp, see EVM user's guide section 3.2.3 for an example.

  • 0 in reply to Noel Fung
    Prodigy 10 points

    Hi Noel,

    Would it be possible to use one of the flags as the oscope trigger and set the oscope in persistance mode to capture multiple triggers to see if it shows any time variation and do a zoomed-in capture with better resolution time base?
    We are also interested in knowing the delay (and hopefully its variation) from the external trigger to the beginning of ramp.
    It'd be appreciated if you also capture Ref signal on the same plot as probably all these signals are sync'd to it.

    We appreciate your help.

  • 0 in reply to Hani Esmaeelzadeh
    TI__Guru* 85740 points

    Hi Hani,

    Do you have a TI sales contact? We should be able to get you an EVM through the sales channel.