• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 20 subscribers
  • Views 202 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPL5111: M_DRV held high at POR

Evan Cornell
Expert 1400 points
Part Number: TPL5111
Other Parts Discussed in Thread: SN74LVC1G125, SN74LVC1G04,

My use case is this:

EN/ONE_SHOT = GND (one shot mode). TPL5111 M_DRV held high by toggle switch (not momentary) so that DRVn is high all the time (keeps load switch enabled to power the system). When switch is toggled, M_DRV will go low, and DRVn will go low after the timer period expires (turning off load switch). Effectively, this is a delayed shutdown circuit. 

What I am worried about is the timer conversion time, if M_DRV is held high at boot, or comes high before the conversion time t_Rext has elapsed, what will that do to the stored timer interval period? 

  • 0
    Expert 1400 points

    If indeed I need to guarantee that M_DRV is not held high at POR to properly digitize the RSET value, then I propose the following circuit, which attempts to allow M_DRV pin to be not affected by switch for about 280ms after supply voltage is applied:

    SN74LVC1G04 keeps the OEn pin of SN74LVC1G125 high, which keeps output of G125 high-Z until 221k/10uF RC circuit charges to at least 0.5V or so (this isn't particularly precise), which shouldn't happen for at least 280ms, plenty of time for TPL5111 to set the timer value.

    Please advise at this approach. Obviously supply current of the two logic gates (10uA each) vastly outstrips the TPL5111 (35nA), but this is acceptable for my application.

  • +1 in reply to Evan Cornell
    TI__Guru* 87690 points

    Hi Evan,

    To play safe, I would put a pull-up resistor at the OEn pin to VSYS_BAT to ensure OEn pin is HIGH when VSYS_BAT is applied. 

  • 0 in reply to Noel Fung
    Expert 1400 points

    Noel,

    I just received TPL5111EVM, and playing around with it, applying VDD while holding down the M_DRV switch, which shorts the DELAY_M_DRV pin to VDD, the part still seems to digitize the timer resistor setting properly. 

    Can you please explain how the part is doing this? If I can confidently understand why that works, then I think I can delete the two logic gates in the circuit above with lesser risk to my circuit. 

    Thanks,
    Evan

  • 0 in reply to Evan Cornell
    Expert 1400 points

    Actually, upon closer investigation, I see that DRVn doesn't assert high until ~65ms after I release M_DRV switch, so presumably the resistor digitization is happening at that point. So I do need my logic gate circuitry to make sure that doesn't happen.