Part Number: LMK04832
Hi Team,
We are planning to use two LMK04832 ICs for synchronization between two systems.
1. Independent reference clock inputs are fed to either of the clock inputs.
2. A common SYNC pulse of 1Hz is generated from FPGA & fed to the SYNC pin of the LMK ICs.
I/P Clock: 155.52Mhz, O/P Clock: 13.824MHz (Synchronized to SYNC pulse).
Hi Arijeet,
Sorry for the delay, I reviewed the schematic and .tcs file and the only potential issue I found is that SYNC is disabled for some of the outputs, I'm not sure if this is intentional.
For your other questions:
1. We don't have an official spec for this in the datasheet, but the SYNC pulse width should be at least 15 distribution path clock cycles (around 6ns for your config)
2. Yes, any output where the SYNC_DISX bit is cleared will be reset during a SYNC pulse
3. You would need to use CLKin1 as your 155.52 MHz input, set CLKin1_DEMUX to 2 to select PLL1, and set CLKin0_DEMUX = 0
4. No, you don't need to use SYSREF for most use cases if you're not using JESD
Let me know if you have any other questions.
Regards,
Connor
Hi Arijeet,
Every time the SYNC pin is toggled, any outputs where SYNC is enabled will be reset and pulled low during the SYNC pulse. Looking at Figure 7 in the datasheet, the output divider circuitry is reset if there is an active SYNC pulse and SYNC_DISX = 0 (SYNC is enabled). This is necessary to make sure that all the synced outputs have a rising edge at the same time.
Just to clarify my earlier reply, this means that the SYNC_DISX (SYNC disable) boxes should be unchecked if you want the outputs to be synced. If those boxes are checked, then the sync function will be disabled for those outputs.
A few comments on your new config file:
1. The "DCC & HS" boxes should be enabled on all outputs since you are using an odd clock divider value. This will make sure that the duty cycle on the output is close to 50%.
2. On the "PLL1 and 2" page, PLL2 RCLK MUX should be set to OSCin if you want to use the XO as the reference for PLL2
Regards,
Connor
