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LMK1D1216: Obtaining ultra low jitter fanout for LVDS signal pulses/ low frequency input

Part Number: LMK1D1216

Hello!

For an implementation with a super fine resolution TDC i am looking for a method of fanning out 1 LVDS input pulse to 16 LVDS pulses in order to do sample averaging on the TDC. 

The implementation of this fanout/repeater may not introduce a lot of jitter, (preferably less than 0.8 ps of total additional jitter from the fanout).

The frequency of this input pulse can be either a single pulse or close to zero but also may be a frequency higher, in theory up to ~ 1Ghz. 

The slew rate of the input signal will not be an issue as it can be configured. 

Now the LMK1D1216 seems like a suitable candidate, it seems like frequencies between DC and 2GHz can be fanned out. 

What I am worried about is the amount of additive jitter that will occur when the input signals are near DC frequency. 

I am wondering if using the LMK1D1216 would be possible for , and if so if there is an estimation of the amount of maximum of additive jitter near DC frequency. 

Maybe my idea of using this LVDS buffer as a signal repeater is not ideal and there is a better solution to doing this? I am very open to hearing alternative solutions!

I am looking forward to ideas!

Thanks in advance!

~ Boris

  • Hello Boris,

    I'll get back to you by the end of the week.

    Best,

    Andrea

  • Hello Boris,

    The LMK1D1216 does seem like the best option as you described. However, because of the limit with our test equipment, both to capture the jitter at those low frequencies and to output a clean enough low frequency signal, we cannot go as low as DC to test this for you. The closet I was able to capture is down to 2MHz, which results in an additive jitter of 37.55ps (from 1-kHz to 1-MHz integration BW to avoid the second harmonic occurring at 2-MHz), which does not seem to meet your requirements. Note that the LMK1D was optimized at higher frequencies, and unfortunately, we do not have another buffer that meets all your requirements.

     

    Best,

    Andrea

  • Hi Andrea, great to hear from you again.

    It seems like buffering my LVDS signal will indeed add to much jitter for my application, so I will have to look further into a different approach.

    I want to thank you for all the effort that has been put into answering my question and the added simulation, it is highly appreciated!

    Have a good weekend and best wishes! 

    ~Boris