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LMX2592: Register changes with new different values for the default bit values and also new parameters introduced in the different Datasheet Revisions

Rolf Demmig
Prodigy 10 points
Part Number: LMX2592

Hi

I do have a question regarding the different Datasheet Revisions for the LMX2592 (latest greatest is Rev. G).

Does the Datasheet Revision correspond to a HW Revision of the Chip? I.e. are there different HW Revisions of the Chip sold from the Production Start up to now? If there are different HW Revisions that need different default register settings, how can I detect the actual HW Revision of the Chip by SW to perform a correct version handling in SW? I did not see any register that would present a Chip HW Revisioning.

If there are no different HW Revisions of the Chip sold from its Production Start up to now, then how would I have to interpret the different values for default bit settings in some registers with respect to the different Datasheet Revisions?

Some examples for the different Register Layouts in the different Datasheet revisions:

* Register 64: Bit Position 4 (counted from 0) up to Rev. C this bit was part of AJUMP_SIZE. From Rev. F this bit shall be set to 1 as default and does no longer belong to AJUMP_SIZE.

* Register 33: Rev. A default value is 0x4210 and starting from Rev. C the default value is 0x2606

* Register 32: Rev. A default value is 0x4210 and starting from Rev. C the default value is 0x2106

* Register 7:  Rev. A default value is 0x20B2 and starting from Rev. C the default value is 0x28B2

Best Regards

Rolf

  • 0
    TI__Mastermind 27641 points

    Rolf,

    These settings are to optimize the performance of the device.  We have undisclosed bits that control various settings that we try to optimize, especially related to VCO phase noise, performance, calibration, ect.  Over the course of time, we may determine that there may be more optimal settings for these bits.  Or perhaps RevA was never right to begin with.  In any case, the change in the default values has nothing to do with the actual silicon changing.

    R64:  This bit was never part of AJUMP_SIZE

    R33:  These are tweaks to optimize the VCO phase noise

    R32:  These are tweaks to optimize the VCO phase noise

    R7: For Bits 10 and 11, these bits do not have any function.

    Regards,
    Dean

  • 0 in reply to Dean Banerjee
    Prodigy 10 points

    Hello Dean

    thanks for your quick reply. I do understand now that changes in the default values are done with respect to enable an optimized behaviour.

    What makes me think is your statement "the change in the default values has nothing to do with the actual silicon changing" which directly corresponds to my initial question "I.e. are there different HW Revisions of the Chip sold from the Production Start up to now?" I can understand that changes in the default values may not be related to different HW Versions (if there are different HW versions out in the field), but the question was also if there were different HW Versions sold up to now, and if so, if they then would need different settings in the available registers. When I read your statement above I would assume there were different HW Versions sold.

    Best Regards
    Rolf

    Btw. Regarding Bit4 in Register 64:

  • 0 in reply to Rolf Demmig
    TI__Guru* 85500 points

    Hi Rolf,

    For this particular register definition revision, I don't know the history well, I may need to spend some time to track back the whole story. One thing I am sure is we have never change the silicon since production.