LMK04832: Questions about LMK04832's specifications

Takemura-san,

First, please note that LMK04832 VCO0 maximum frequency guaranteed is 2580MHz; if 2600MHz is required, most devices (but likely not all devices) can achieve this frequency, and the full range of temperature calibration may be reduced for devices that can achieve this frequency (see Allowable Temperature Drift for Continuous Lock section in the datasheet electrical characteristics).

Now, your questions in order:

Taito Takemura said:

They are assuming a 2.6GHz output as the ADC sampling clock, but what is the required input frequency? Is it either 0.001-250MHz?

LMK04832 is a PLL, so the input frequency has a large range of potentially acceptable values. The restrictions can be summarized as:

• Must share an integer divisor frequency with the VCO frequency (e.g. 125MHz and 2600MHz share 25MHz as a common divisor; 100MHz and 2600MHz share 100MHz as a common divisor; etc); this common divisor is used as the phase detector frequency
• Generally try to maximize the phase detector frequency for better phase noise performance - PLL noise performance in the midrange offsets (about 10kHz to 400kHz) improves by 10 * log(Fnew / Fold) dB per octave (doubling) of the common divisor frequency, so in the examples above, the 25MHz phase detector would perform about 10 * log(100/25) = 6dB worse than the 100MHz phase detector
• Sometimes reference frequency and desired frequency have a very small common divisor - for instance, if reference frequency is 122.88MHz and desired output is 2600MHz, greatest common divisor is 320kHz, which is a 25dB performance loss compared to a 100MHz reference. If available reference frequencies are too restrictive, PLL1 can be used with low loop bandwidth and a clean VCXO to provide a reference with lower phase noise above PLL1 loop bandwidth to PLL2 input. So with 122.88MHz reference, instead you could make PLL1 loop bandwidth 100Hz and use a 100MHz VCXO; even though the greatest common divisor frequency at PLL1 is only 160kHz, the low loop bandwidth filters the PLL and reference noise leaving only the 100MHz VCXO noise, which can be cascaded into the input of PLL2 to achieve much better performance. This same trick can also be used with a higher-frequency reference that has worse phase noise performance - the reference will be filtered above PLL1 loop bandwidth, so reference noise above the PLL1 loop bandwidth will not be added to the final output.
  
  But if the reference has decent phase noise and is available at a good frequency, for instance a 100MHz reference from an XO, PLL1 can be disabled in register settings and PLL2 with integrated VCO may be used alone, and performance will not be impacted. I think this is probably your customer's use case, but check with them first.

In summary, flexibility in input frequency is provided for cases where it is either required or necessary, but typical use cases don't need a broad input frequency range and can pick a normal value like 100MHz as the reference frequency to PLL2. PLL1 is an option to help if the system reference frequency shares a very small common divisor with the desired VCO frequency, or if the reference noise is not very good. But if the reference has good phase noise performance and is at a good frequency, PLL1 is not needed or recommended.

Taito Takemura said:

It is a question regarding the dynamic phase adjustment function. How long does it take for the register to be actually shifted by half a clock after being rewritten via SPI communication?

We do not specify any guaranteed timing characteristics for the half-step adjustment period. On the last data bit clock cycle rising edge of a SPI write transaction, the new data to the SPI registers is latched into register state. An internal state machine clock running at nominal 10MHz ± 30% propagates the change across the SPI domain and into the internal register state machine domain, which takes some single-digit number of state machine clock cycles (varies depending on timing variation between internal state machine clock and SPI clock). Once the half-step register result is propagated into the internal register state machine domain, it should only take one or two VCO cycles for the half-step to engage. So I think, from last data bit clock cycle rising edge of SPI to half-step phase adjustment complete, timing is in the range of (0.3µs to 1µs) + (1 to 2 VCO periods), but there may be other factors of which I am unaware. If a more precise answer is required, or if additional verification is needed, please let us know.

Taito Takemura said:

I think that it is possible to output a trigger signal from the LMK04832,and could you please tell me the shape of signal waveform? Is it pulse-like?

The SYSREF outputs can be used to generate one or more pulses with width equal to the 2/(F_SYSREF). The pulser synchronously outputs full cycles of the SYSREF divider, so setting the SYSREF divider value controls the pulse width.

Regards,

Derek Payne