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LMK04808: Inquiry regarding normal clock output even if reference clock (OSCin) is not input after PLL Lock

Lee HongGyo
Prodigy 220 points
Part Number: LMK04808

I'm using LMK04808.
I would like to inquire because I have any questions regarding the operation of LMK04808.
The LMK04808 configuration is used as a Single PLL mode configuration (PLL2, Internal VCO).
OSCin is used for PLL reference input.
All 12 channels from LMK04808 clock output 0 to 11 are in use.
After turning on the power to LMK04808, the clock is output well at the set value.
In this state, the LMK04808 clock output is normal even without inputting the PLL reference clock (OSCin) (except for ch 6 and 7).
I understand that ch6 and 7 are not output because they are divide type output from OSCin.
Except for ch6 and ch7, the remaining channels are continuously output even without inputting the PLL reference clock (OSCin).
I would like to know why clock output continues even if the PLL reference clock (OSCin) is not input after PLL Lock.

  • 0
    TI__Expert 6901 points

    Lee, 

    I will get back to you tommorow,

    Will

  • 0 in reply to William Pfennigwerth
    Prodigy 220 points

    Hi William

    I haven't received a reply yet.
    Please confirm.

  • 0 in reply to Lee HongGyo
    TI__Expert 6901 points

    Lee, 

    Sorry for the delay, I will get back to you by the end of the week.

    Regards,

    Will

  • 0 in reply to William Pfennigwerth
    TI__Expert 6901 points

    Lee, 

    Lee HongGyo said:
    I would like to know why clock output continues even if the PLL reference clock (OSCin) is not input after PLL Lock.

    When outputs are not in a power down state they will continue to output a frequency coming from the internal VCO.  CLK8 for example will output ~ 110 MHz signal on powerup, when no PLL's are locked and with no OSCin.

    If you would like to have your outputs be powered down when lock is not achieved you can turn on SYNC_PLL2_DLD.  This will keep the outputs low when PLL2 is not locked.  

    Regards,

    Will

  • 0 in reply to William Pfennigwerth
    Prodigy 220 points

    Hi William

    My question is why the output continues normally even though the reference clock is not supplied after locking.
    I expected that there would be no output if the reference clock was not supplied after locking. However, contrary to my thoughts, the output continues to come out.

    I look forward to your kind explanation once again.

    Thanks and Best regards,

    Lee HongGyo

  • 0 in reply to Lee HongGyo
    TI__Expert 6901 points

    Lee,

    Even when the PLL is not locked, the VCO will still output a frequency.  When the reference is lost, the PLL loop will try to account for this difference in frequency between the input and VCO output and will therefore vary the VCO frequency to some degree but not disable it.  

    Regards,

    Will

  • 0 in reply to William Pfennigwerth
    Prodigy 220 points

    Hi William

    Hi Will
    Thanks for your explanation.
    You explained that the clock comes out even when the reference clock is lost after PLL lock.
    Is LOCK maintained in LMK04808 when the reference clock is lost?
    Is there any way to know that LMK04808 has lost its reference clock?

    Thanks and Best regards,

    Lee HongGyo

  • 0 in reply to Lee HongGyo
    TI__Expert 6901 points

    Lee,

    In your single loop configuration, if you lose the reference clock, then you will lose lock.  Yes there are a few different ways to know that you have lost lock.

    The first option is you can enable SYNC on the digital lock detect (DLD) of PLL2 which will put the output into a sync state which turns the output off.

    William Pfennigwerth said:
    If you would like to have your outputs be powered down when lock is not achieved you can turn on SYNC_PLL2_DLD.  This will keep the outputs low when PLL2 is not locked.  

    Another option, easy to use on the EVM, is to use the some of the I/O ports on the device to signal on PLL2 DLD.  This is the case on the EVM because in the standard configuration the LD_Mux, which controls an LED is set to DLD.  

    Let me know if you have any further questions,

    Will

  • 0 in reply to William Pfennigwerth
    Prodigy 220 points

    Hi Will

    1. In your single loop configuration, if you lose the reference clock, then you will lose lock.
    However, my measurements were different from your description.
    The lock signal remains high even if the reference clock is lost.
    Our register R12 settings are as follows.
    LD_MUX=PLL2DLD
    LD_TYPE=Output (push-pull)
    The measurement point is IC pin 33 Status_LD.

    2. SYNC_PLL2_DLD was set to low.
    I will measure it using SYNC_PLL2_DLD high.

    Please check again regarding item 1.

    Thanks and Best regards,

    Lee HongGyo

  • 0 in reply to Lee HongGyo
    TI__Expert 6901 points

    Lee,

    I will look into that on the bench, and get back to you.

    Regards,

    Will

  • 0 in reply to William Pfennigwerth
    TI__Expert 6901 points

    Lee,

    I tested this on our EVM with the same settings you mention as above and was unable to replicate your issue.  When I powered on the device with the reference powered off STATUS_LD of pin 33 was low, when I powered the reference signal on, STATUS_LD was high, and again when I turned it off, STATUS_LD went low.  This is the expected behavior.  

    A few things to check:

    • Ensure the LD_TYPE is set to Output Enabled (push-pull driver)
    • Ensure your reference signal is completely lost when you expect it to be off
      • Probe your reference with an oscilloscope, and ensure there is no output
    • Ensure STATUS_LD is not high when there is no reference input (instead of removing it after powering on, remove it before powering on) - this would help us narrow down the problem and would be unexpected behavior

    Regards,

    Will

  • 0 in reply to William Pfennigwerth
    Prodigy 220 points

    Hi Will

    There seems to be some confusion about the conditions of your experiment.
    The conditions for my experiment are that when the reference clock is supplied normally, all clock outs occur normally. And LD is normally maintained at high. In this state, the reference clock supply is removed.
    And at this time, the status of STATUS_LD is checked.
    At this time, please show the results of the reference clock and STATUS_LD measured with an oscilloscope.
    Please try the experiment again under these conditions.

    Thanks and Best regards,

    Lee HongGyo

  • 0 in reply to Lee HongGyo
    TI__Expert 6901 points

    Lee,

    William Pfennigwerth said:
    I powered the reference signal on, STATUS_LD was high, and again when I turned it off, STATUS_LD went low

    I did perform this experiment, but I will capture a oscilloscope plot for you today.  

    Regards,

    Will

  • 0 in reply to William Pfennigwerth
    TI__Expert 6901 points

    Lee,

    Here is a scope capture showing the reference (shown as osc_out, buffered from osc_in), the status_ld state when set to PLL2 DLD and CLKout6 with SYNC_PLL2_DLD enabled which forces the output to low when PLL2 lock is lost.  

    Let me know if you have any further questions and if you can replicate this on your end.  

    Regards,

    Will

  • 0 in reply to William Pfennigwerth
    Prodigy 220 points

    Hi Will

    Thanks for your experiment.
    I keep asking questions because I think your experiment and my requirements are different.
    I have been thinking about the conditions under which you experimented.
    I'm guessing you've probably experimented with PD_OSCin in Register R10.
    If PD_OSCin is '1', STATUS_LD changes to Low.
    If PD_OSCin is '0', STATUS_LD changes to High.
    This is also reproduced on our experimental board.
    However, my request is not to use PD_OSCin, but to remove the reference clock.
    In other words, why does STATUS_LD not change when PD_OSCin is kept at '0' and the reference clock is not provided externally?
    Please check with EVM again.
    Is there a way for LMK04808 to know when the external reference clock is lost?
    If my guess (Register R10 use) is wrong, please provide the LMK04808 register value you used.
    Please provide register values from R0 to R31.

    Thanks and Best regards,

    Lee HongGyo

  • 0 in reply to Lee HongGyo
    TI__Expert 6901 points

    Lee,

    I understand.  I did not use PD_OSCin to turn off the reference.  My reference to PLL2 is driven by the EVM's VCXO.  To disable the reference, I removed the power supply to the VCXO, which then caused STATUS_LD to go low.  I have attached my .tcs and register values for my configuration. 

    Regards,

    Will

    RegisterValues_122.88_ref_singleloop.txt 
    R0 (INIT)	0x80160180
R0	0x80140180
R1	0x80140181
R2	0x80140182
R3	0x00140183
R4	0x00140184
R5	0x80140185
R6	0x04040006
R7	0x08010007
R8	0x04010008
R9	0x55555549
R10	0x9842410A
R11	0x0401100B
R12	0x138C006C
R13	0x2302826D
R14	0x0200000E
R15	0x8000800F
R16	0xC1550410
R24	0x00000058
R25	0x02C9C419
R26	0xAFA8001A
R27	0x10001E1B
R28	0x00201E1C
R29	0x0180019D
R30	0x0200019E
R31	0x001F001F
    122.88_ref_single_loop_mode.tcs

  • 0 in reply to William Pfennigwerth
    Prodigy 220 points

    Hi Will

    Thank you for the quick response.
    I will compare it with our board using the register value you sent.
    Thank you again.

    Thanks and Best regards,

    Lee HongGyo

  • 0 in reply to Lee HongGyo
    TI__Expert 6901 points

    Lee,

    Of course, let me know.

    Regards,

    Will

  • 0 in reply to William Pfennigwerth
    Prodigy 220 points

    Hi Will

    With your help I was able to find our incorrect register settings.
    In summary, I was using incorrect register settings as shown below.
    R11 EN_SYNC=1, R12 SYNC_PLL2_DLD=0
    With this set up,
    If the reference clock is lost during normal operation, STATUS_LD remains high and output continues to be output.
    I set both EN_SYNC and SYNC_PLL2_DLD to high and continued the same experiment. As a result, STATUS_LD changed to Low and output stopped.
    The contents of the experiment are summarized in a table as follows.

    Thank you again so much for your help.

    Thanks and Best regards,

    Lee HongGyo

  • +1 in reply to Lee HongGyo
    TI__Expert 6901 points

    Lee,

    Of course, I am very happy that you were able figure out the problem.

    Regards,
    Will