LMK5B33216EVM: Frequency- and phase- adjusted 10 MHz

Hi Rob,

Let me look into this and get back next week.

Some questions:

1. How much ppm adjustment/correction are you making through the DCO?
2. I do not see an output on OUT0. Could you please issue a software reset (located as a button in the toolbar) to see if that gets you a toggling output?
3. "We assume that the value given here is just to set the different DPLL/APLL parameters and, given that DPLL2 only has to output a signal with the same frequency as the input, it will not complain. Is this correct?"
   1. Correct. The APLL numerator is the initial state, at start-up (when in holdover) before the DPLL becomes active and starts making the corrections based on the IN0/IN1 phase. The DPLL LOPL and LOFL flags are determined by the ppm thresholds set in the Validation page. If the reference frequency deviates beyond the expected ppm thresholds, the the LOPL/LOFL flags will stay set.
   2. 

Regards,

Jennifer

Hello Jennifer,

Thanks for your quick reply!

1. the RF systems we are controlling has quite accurate oscillators, let's bound their precision to +-0.2 ppm @ 25 MHz, so at most +- 5 Hz (though typically way smaller than that, the highest value I've experimentally observed in more than 1 year was slightly below 2 Hz)

2. actually that was something weird: once I write the registers an output is shown, though it has the wrong frequency. As soon as I hit the software reset, the output disappears, and nothing I can do is able to restore it. Sometimes having the board power cycle + disconnecting the USB and then redoing the programming again, gets back the output, but with the same phenomenon (i.e., when I do the software reset, the output is gone forever). This does not happen if I use a single output, with no loopback, so this is definitely related to a misconfiguration.

3. perfect, thanks for the info!

Looking forward to hearing from you!

Have a nice weekend!
Rob

Thank you for the update. I will review next week as mentioned.

Regards,

Jennifer

Dear Jennifer,

I wonder if you had time to have a look at the issue I encounter, and if further tests are required from my side to give you additional information. I will be at the office tomorrow and so I'll be able to perform them (next week I will be away for mandatory training, so I won't be able to access the board until next Friday).

Thanks a lot and have a nice day!

Best,
Rob

Hello Jennifer,

I've accidentally discovered that the absence of the output is linked with the "Bypass" and the "Doubler" options being checked in the VCO3 feedback for DPLL2 in step 1 --- if I remove both of them, the APLL frequency drops to ~104 MHz, but I see the waveforms as output. However, even though the waveform seems to be very stable on the oscilloscope, it never locks in the status page.

The configuration I've created for this is this one:

rob_almost_working.tcs

(please note that I've changed OUT4 for OUT1 as an intermediate output --- the hw had been changed as you've instructed me in a previous post to have a proper CMOS output on OUT1_P).

Possibly as a consequence of the lack of lock, it seems to be impossible to alter the phase of DPLL2 via ZDM --- the waveform for the final output does not move a bit.

Do you have any idea for the above?

Thanks again for your help and have a nice week-end!

Best,
Rob

Hi Rob,

My apologies, I meant to reply yesterday and didn't hit send!

Can you please try with this configuration file? This setup is based on your block diagram.

LMK5B33216_XO=48MHz_REF=10MHz_OUTs=10MHz, VOD=800mV, zdm.tcs

However, I do have some additional comments about your block diagram:

1. APLL2 outputs will have deterministic phase (zero-delay) with APLL3 outputs (cascaded into IN1) but will not have deterministic phase with IN0 (the DPLL3 input).
2. Here is a broken down view of your block diagram.
   1. 
3. Here are some scope shots of the configuration. You can see that the yellow (DPLL2/OUT0) and pink trace (DPLL3/OUT10) have zero-delay with each other but not to IN0 (sig gen). With that said, OUT0 and OUT10 are synchronized with IN0 (meaning the outputs will track and folllow the phase and frequency of IN0).
   1. Time = A (random) , after issuing a software reset.
      1. 
   2. Time = B (random), after issuing a software reset.
      1. 
4. Can you please elaborate further why you need ZDM for your use case?

Regards,

Jennifer

Dear Jennifer,

No worries, thanks for your reply!
I've quickly tried your design before leaving for the training and it performs similarly to the design I've joined to my latest posts, but it looks like I cannot alter the phase of DPLL2. The diagram in (2), however, does exactly what I do in the above-mentioned design (I use OUT1 instead of OUT10, but the rest is the same), so I'm happy that I didn't stray too much :)

1+4. Yes, this is what we want to achieve. The idea is that IN0->OUT1 uses DCO to adjust the frequency, while IN1->OUT0 adjusts the phase via ZDM. Our goal is to have a 10 MHz signal controllable both in frequency and in phase via I2C (e.g., we would like to be able to just say "ok, increase the frequency of the signal currently output by OUT0 by 1.23456 Hz and the phase by 7.89 ns"), the absolute frequency of the input coming from the signal generator is uninteresting to us --- the 10 MHz output by OUT0 is then fed into an SDR where it gets transformed in a 25 MHz signal, and we want this 25 MHz signal to be "perfectly" synchronized with the 25 MHz used by another SDR device.

Things start to work, now I just wonder why bypassing the R divider & doubler for APLL2 seems to prevent all the PLLs in the board to lock. Do you have an explanation for that, please?

Thanks again for your help and best regards!
Rob

Hello Jennifer,

Sure, when I'll be in my office on Friday I'll try them!
Thanks and have a nice day!

Best,
Rob

Hi Rob,

Sounds good, I'll look out for your reply.

Regards,

Jennifer