LMX2820EVM: Lock Detect(LD) Time Question

JAEHOON KIM

Part Number: LMX2820EVM

Hello.

I am curious whether the time from SPI CSB to Lock Detect can be within 50us when initially setting the PLL frequency to 12GHz with the LMX2820EVM board and sweeping (up or down) in 0.5Mhz increments.

48MHz will be input into OSCINP, and SPI CLK will be controlled at 24MHz.

It is required for system review (make sure the time from SPI CS#(39PIN) to Lock Detect(38PIN) is within 50us). Could you do an experiment for me?

Thank you

J.H. KIM

8 months ago

0 Noel Fung 8 months ago

TI__Guru* 94640 points

Hi Kim,

The total lock time is equal to (1) programming time + (2) VCO calibration time + (3) PLL analog lock time.

If we change the VCO by 500kHz, we can skip VCO calibration. Total lock time = (1) + (3). PLL analog lock time depends on the loop bandwidth, a rough estimation is lock time = 4/loop bandwidth.

After the VCO has accumulated a substantial amount of frequency change, a VCO calibration is required to ensure the VCO frequency can continue to be change. Total lock time = (1) + (2) + (3). VCO calibration time depends on some of the VCO calibration register settings.

We can also use "full assist" to skip VCO calibration, this way the total lock time is always equal to (1) + (3).

To understand VCO calibration and full assist, please read below application note.

Clock & timing

Clock & timing forum

LMX2820EVM: Lock Detect(LD) Time Question