LMK05028: Problem getting PLL2 to both phase and frequency lock to IN0 ref input.

Hello Gary,

I will begin working on this and try to understand what is happening. I will update you again by the end of this week.

Best Regards,
Kyle Yamabe

Hello Gary,

I wanted to confirm but are the XO and TCXO values swapped? The default on our EVMs are a 10MHz TCXO and a 48.048MHz XO.

Also looking at the configuration for Step 3 the input select mode, have you tried changing the auto select to ignore or changing the select mode to manual then selecting the register to reserve?

I am also curious why you have connected OUT6_P (sourced from PLL1) to IN0_P? This is just to help me understand how to best create a new configuration.

Thank you so much

Best Regards
Kyle Yamabe

Hi Kyle,

Thank you for your help in looking at this problem.

Apologies for the typo. Oscillator frequencies are as per the EVM defaults: TCXO = 10MHz, XO = 48.0048MHz.

For the configuration in step 3, the ‘auto’ setting is for DPLL1 (REF-DPLL1 I believe) which I am not using. PLL1 should be running in 2-loop, TCXO/APLL mode so the outputs from PLL1 should be locked to the TCXO frequency. I hope I have understood this correctly.

I want PLL2 to run at 156.25 MHz and to be able to phase lock to 3 possible reference clocks. These are 156.25 MHz, 125 MHz and 62.5 MHz. All three clocks are recovered clocks, with the exception of the 156.25 MHz which can also be sourced directly from PLL1. The previous engineer working on this connected this locally sourced 156.25 MHz externally to the PLL IC, hence OUT6 is connected to IN0. I believe this connection should be able to be made internally, possibly by setting PLL reference input to ‘VCO1 Loopback’.

For my initial tests I just wanted to lock PLL2 to PLL1 using this external connection via IN0. Once I had this working I planned to add the other frequency options.

Best regards,
Gary

Hello Gary,

Sorry for taking longer to get back to you about this question.
I have been setting up your system and testing the board and I see the same issues you described with the PLLs not locking.
I will try to figure this out early next week.

I did have a question, what are the output frequencies from PLL1 are you getting exactly or close to 156.25MHz on OUT0, OUT1, and OUT2?

Best Regards,
Kyle Yamabe

Hi Kyle,

I have just checked the frequencies from PLL1 and PLL2. PLL1 is generating 156.62 MHz, while PLL2 is generating 156.58 MHz.

I have confirmed the measured frequencies by using the same scope to measure the output from a Keysight Pattern Generator set to generate an output frequency of 156.25 MHz. This measures 156.249 MHz on the same scope.

I have also connected the pattern generator output to reference input IN0 and routed this through to OUT0. This measures 156.247 MHz. I think this proves that my reference input configuration is correct.

It looks like neither PLL is generating the frequency it is configured for.

Best regards,
Gary

Hello Gary,

Thank you for confirming that information with me. I was also seeing the outputs not set correctly on my setup so there is an issue with the set frequency causing the outputs to not be correctly configured.

Since the frequencies are not locked to the actual set frequency it is causing the phase and frequency locking issues for the system.

I will work on debugging why the outputs are not properly setting the output frequencies which should solve the locking issues.

Best regards,
Kyle Yamabe

Hi Kyle,

I have managed to get PLL1 to generate the desired 156.25 MHz output frequency. I did this by changing the TCXO Loop Bandwidth from 600 down to 20.

I have also experimented with the configuration for PLL2. I have changed the mode from 3-loop to 2-loop, REF-DPLL. This again gives me the correct 156.25 MHz output frequency and after setting the DPLL Loop Bandwidth to 20 and playing around with the phase and frequency lock thresholds, now phase and frequency locks to the reference inputs as well.

Since I am after good jitter performance from PLL2, I imagine 2-loop, REF-DPLL mode is suitable for me. However, I would still like to get 3-loop mode running as this should give me better frequency stability. I have tried different TCXO Loop Bandwidth settings with PLL2 in 3-loop mode, but have failed to get 156.25 MHz at the output. It remains around 156.60 MHz. Have you made any progress on a better configuration for this setup?

I have attached my latest TICS Pro configuration file with PLL1 in 2-loop, TCXO-DPLL mode and PLL2 in 2-loop, REF-DPLL mode.

Best regards,
Garymy_dev_bd_07-11 PLL2 2-loop mode all locked.tcs

Hello Gary,

I am still working on generating a configuration I will generate a configuration for you by the end of day tomorrow. I will also work on getting the best jitter performance from PLL2.

Best Regards,
Kyle Yamabe