LMK05028: Further problem with getting PLL2 to lock to a reference input when configured in 2-loop, REF-DPLL mode.

Tool/software:

Hi,

Further to my original question “LMK05028: Problem getting PLL2 to both phase and frequency lock to IN0 ref input” on 29-Oct-24, I now have another problem. PLL2 is configured in 2-loop REF-DPLL mode.

I want to use the 4 reference inputs for PLL2 and have started my tests using the LMK05028 evaluation board, using the DIP switches to change the ref input selection.

IN0 is connected to an output from PLL1 running at 156.25 MHz. PLL2 locks correctly to this reference clock.

IN1 input is configured to lock to a frequency of 62.5 MHz. If I generate this frequency using PLL1 and connect it to IN1 input, PLL2 locks correctly. However, if I connect this to an external source (another board of our design or a frequency generator), then PLL2 will not lock (APLL2 generates the correct frequency, but REF-DPLL2 will not frequency or phase lock).

We have the LMK05028 device on a board of our design. I have essentially the same PLL configuration programmed onto two of these boards, the two boards being connected together using optical fibre. One of the boards uses the output from PLL1 to drive an SFP module. The second board recovers the clock from its SFP module (62.5 MHz) and inputs this as a reference to IN1 of PLL2. The idea being that I can then run the processing on the second board using a 156.25 MHz clock which is locked to the 62.5 MHz recovered clock.

In my test setup using two boards I get the same results as when using the evaluation board. I can get PLL2 to lock if I provide it with a reference from it local PLL1. However, as soon as I source the recovered clock from the other board, then PLL2 will no longer lock.

I currently have the input monitors disabled. Are these only used to generate the various lock flags or do these have an impact on the operation of the PLL as well?

Do the DPLL Frequency/Phase lock detectors only affect the lock flags or do they impact the PLL operation as well?

Unfortunately, I only have one evaluation board otherwise I could try a setup with two boards linked to each other.

Best regards,
Gary

dev_bd_PLL2_2-loop_19-11.tcs