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LMK05028: 1PPS Phase and frequency lock issue

Part Number: LMK05028

Hello,

I am currently using the LMK05028EVM with 1Hz PPS input to generate 122.88MHz output (with an 20MHz OCXO 50ppb stability). We are having an hard time getting a good phase and frequency lock on DPLL1/2. I can see that the duty cycle on the 1Hz input make a big difference on how easily the REF-DPLL can lock.

What values should i use into DPLL Frequency and phase lock detectors for 1Hz input? 

Please find attached the TICS pro configuration file for reference.

Thanks.

LMK05028.tcs

  • Hello, 

    I see these seem to be significantly relaxed already. DPLL lock detect is already past 1000 ppm... typically with a 1 Hz source we're using 0.1 unlock ppm detection, so this orders of magnitude relaxed and I'm not sure that's the issue. 

    Is the reference valid and selected per the status readback? 

    Can you monitor n div and r div path, are they in phase or 180 degree phase shifted? 

    Note frequency lock may take up to 1 minute and phase lock will take several minutes with 1 pps - so please make sure you're waiting long enough. 

    Lastly, what are the accuracies of the TCXO and XO used? 

    Thanks and regards,

    Amin 

  • Ok, I will try to switch to another GPS source to confirm if it's comming from this.

    We are using the XO from the eval board and a custom OCXO 20MHz with 50ppb stability.

    Could you give us some typical value for :

    DPLL frequency lock threshold = 0.1 ppm

    DPLL frequency  unlock threshold = 1?? ppm

    DPLL phaselock threshold = ?? ns

    DPLL phaseunlock threshold = ?? ns

    Thanks.

  • Here are my recommendation steps for locking 1 pps - note I don't think the flag indicators are the best way to do this: 

    1. Start with EVM default configuration - menu option: Default configuration --> EVM default 
    2. Provide inputs in steps 1 - 6 as need and then perform a runscript 
    3. Post runscript perform a status readback: Is reference valid? Is reference selected? 
    4. Monitor R divider and N divider path on stat0 and stat1 - are the signals aligned or 180 phase shifted? Are they approaching that position
    • Once aligned you can be certain DPLL is locked 

    Frequency detectors should not need any adjustment. My experience has been frequency detector works as anticipated from what runscript provides. 

    Phase detector will need adjustment, hence monitoring Rdiv and Ndiv to confirm lock and not depend on status flags that by adjusting these counters could easily be misleading. Once you can observe Rdiv/Ndiv are aligned (or 180 phase shifted) increase phase detector until flag corresponds - this usually involves increasing until ~ 5.5+ ns for lock threshold and ~1.5+ ns for unlock threshold.

    I would advise a few soft resets and proper waits to observe behavior of both the flags as well as actual Rdiv/Ndiv alignment. 

    Thanks and regards,

    Amin 

      

  • Thanks for your help.

    I will try this when possible.

    I was able to validate the PPS input but still can't get a frequency/phase lock with default setting from EVM.

    I think i have an issue with my OCXO or PPS jitter.

    Cyril.

  • Hi Cyril, 

    Just confirming we're on the same page... the "Validate PPS input but still can't get frequency/phase lock with default setting from EVM" comment through me off. 

    So EVM default configuration is not for a 1 PPS input - it is for 25 MHz. The reason I asked you to start there is because not all registers update after a runscript, so in order to avoid any bad starting point or bad register configruation, it's good to start there AND then make changes and needed. 

    The picture of the Main:Start page is at the bottom of this post - after loading EVM default, make changes in steps 1-6 as needed and then do runscript. Then try all the debug steps I've suggested above after script is run and the registers are updated per your specific inputs. 

    Thanks and regards,

    Amin 

  • No worry, i did this. That's how i got the 1PPS input to validate :)

    Cyril.