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LMX2594: External 10MHz Clock Implementation on LMK04828 on RFSoC4x2

Danilo A.
Mastermind 28700 points
Part Number: LMX2594
Other Parts Discussed in Thread: LMK04828, USB2ANY,

Tool/software:

Hi Team,

Can you please help us with our customer inquiry below.

We are trying to enable CLK_IN_0 (image 1) to have a 10MHz signal sync with the device. Looking at TICS and PYNQ forums

https://discuss.pynq.io/t/xrfclk-configuration-lmk04828-using-external-10mhz-reference-clock/5562/12
 
https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1229913/lmk04828-taking-driving_clock-from-another-input-pin-and-i-can-t-figure-out-which-one/4661353#4661353 

I came across 3 different solutions. Provided are .txt files for hex import for each. Using TICS PRO, I am trying to configure our board to have a 10MHz external clock control while disabling OSCin internal referance clock. The other frequencies on the image should remain the same. I don't want to program the board by using USB2ANY cable with any of these .txt files for hex import because we don't have the default LMK04828 .tcs file for the RFSoC4x2. Can you please help us on how we can proceed? We are really stuck and Real Digital didn't provide us the default LMK04828 file for the board. 

Regards,

Danilo

  • 0
    TI__Mastermind 28001 points

    Let me try to understand this:

    1.  You are using a 3rd party board that has the LMK04828

    2.  You are not sure what the settings are for this board for the LMK04828

    3.  If you knew the settings for the LMK04828, then you could use TICSPRO, but provider of the board (Real Digital), is not giving you this information.

    With TICSPRO, you can export and import hex registers to other tools and this does not require you to have TICSPRO hooked up to the board.  If TICSPRO is hooked up to the board, you can also read back the register states.  

    Or if you are asking for a configuration file based on the frequencies in the above diagram, we can provide that.  However, to do this we need:

    With your frequencies, I think you want the VCO to be 2949.12.  You could use the 160 MHz OSCin value, but this will lead to a very low phase detector frequency, which will work, but yield not very good perforamnce.  It would perform much better with a differetn OSCin frequency like 122.88, but this is a hardware change.

    Regards,
    Dean

    Regards,

    Dean

  • 0 in reply to Dean Banerjee
    TI__Mastermind 28700 points

    Hi Dean,

    Please see our customer's response below.

    Thank you for your answer,
    1. We are using RFSoC4x2 board, we are tying to eliminate the phase delay for ADC-DAC signal processing by locking the phase with a signal generator at 10MHz from Ext. Ref. Clk. (CLK IN0)
    2. We don't know the default LMK04828 for this board apart from the data sheet provided in Figure 5.

    3. We connected USB2ANY to the board and read the register values however, they didn't match with what they have on Figure 5. We think that is possible since USB2ANY doesn't connect directly to LMK but instead to Skyworks Si5395.

    RFSoC 4x2 Reference Manual available online : https://www.realdigital.org/downloads/15456c97a4fe5a1ee66208c5aa3894bb.pdf
    Therefore I don't think we can modify OSCin Value of the boards. The frequency requirements are clkin0 should be 10MHz, clkin1 should be 100MHz, OSCin should be 160MHz.
    The clkouts of LMK should be same with figure 5 provided in my initial question. It would be great if you can provide a .tcs file with this requirements, we are new to TICSPro and not sure if the following work.
    Currently, our design is as follows:
    CLK_in & PLLs
    CLK Outputs:
    I want to double check if this design would work before writing it to LMK since we don't have the register values. Thank you for your answer.
     
    Regards,


    Danilo
  • 0 in reply to Danilo A.
    TI__Guru** 107810 points

    Hi Danilo,

    first of all, although the board was not design by our customer, I have doubt to the block diagram.

    7.68MHz clocks have to be generated by the SYSREF block of LMK04828, as the clock divider is not big enough to support 7.68MHz. This is fine as long as the SYSREF block is configured as Continuous SYSREF output.

    OUT4 and OUT1 are used as the SYNC signal to LMX2594, SYNC signal is a single pulse so it also have to be generated by the SYSREF block of LMK04828. However, in this case, the SYSREF block needs to be configured as Pulser mode. 

    That means, OUT3 and OUT9 will be a pulse instead of continuous clock when we attempt to synchronize the LMX2594 devices. 

    Back to the LMK04828 configuration, here is the configuration.

    The 10MHz clock needs to be square wave, otherwise PLL1 may not lock. Use a square wave clock and set the input type to MOS. 

    Use the register next to PLL1 R Dividers to select CLKin1 or CLKin0.

    Configure SYSREF to Continuous clock mode.

    example output configuration, you may need to select the correct output format based on the board design.

    here is the tcs file.

    7652.lmk04828.tcs

  • 0 in reply to Noel Fung
    TI__Expert 8880 points

    Hi Danilo,

    To add to what Noel said, in order to achieve phase synchronization between the input and output signals, you will have to put the device into zero-delay mode. I have attached a tcs file that does that, you will just need to update all of the outputs as you see fit. However, the phase noise performance will be suboptimal due to the numbers that the configuration will have to support - as Dean mentioned, it would be better if the VCXO frequency were 122.88 MHz.

    lmk04828_rfsoc.tcs

    Furthermore, in order to achieve the deterministic phase relationship between the input and output, you will need to generate a SYNC event. Section 9.7.3.10 provides an overview of how to generate one. The SYNC event results in all of the output dividers being phase aligned, and you will have achieved your necessary clock tree and input output relationships.

    Thanks,

    Michael

  • 0 in reply to Michael Srinivasan
    TI__Mastermind 28700 points

    Hi Noel and Michael,

    Thank you for your help. We have 3 more questions regarding this. I modified the zero-delay rfsoc file to match with our required clock output values and also enabled continuous SYNC for deterministic phase relationship. Here is how it looks right now.

    We have a few more questions.

    1- The first .tcs file you provided has a different internal VCO clock compared to the zerodelay .tcs file. (2457MHz / 2949MHz). As long as the output clocks have the right frequency, does the internal VCO clock's frequency matter?

    2- I modified SYNC/SYSREF to be in continuous SYSREF mode referencing from the section you mentioned, I think this mode should continuously align the phases. Also, the selected clock input for PLL1 should be CLK0 since that's where the signal generator's 10MHz will be connected. Are these right assumptions?

    3- PLL1 and PLL2 are both locked in this configuration. Before continuing to test this .tcs file with our RFSoC4x2 board and signal generator. Is it possible for you to check/verify the accuracy? I attached .txt file for raw register values. Real Digital doesn't reply back to our emails. We want to make sure to have the correct configuration.

    Fullscreen 6303.HexRegisterValues.txt Download
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12
    13
    14
    15
    16
    17
    18
    19
    R0 (INIT) 0x000090
    R0 0x000000
    R2 0x000200
    R3 0x000306
    R4 0x0004D0
    R5 0x00055B
    R6 0x000600
    R12 0x000C51
    R13 0x000D04
    R256 0x01000C
    R257 0x010155
    R258 0x010255
    R259 0x010301
    R260 0x010422
    R261 0x010500
    R262 0x0106F0
    R263 0x010711
    R264 0x01080C
    R265 0x010955
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Regards,

    Danilo

  • 0 in reply to Danilo A.
    TI__Expert 8880 points

    Hi Danilo,

    1. Preferably, you would use 2457.6 MHz as your VCO frequency, as this will require a lower N divider value, which will reduce the phase noise.

    2. Continuous SYSREF (while the correct SYSREF configuration)will not automatically align the phases, you must perform a SYNC event to achieve that. Also, yes, you should select CLKin0 as the driver of PLL1 if that is the input for the 10 MHz signal. 

    3. I cannot test your exact configuration on my board, as our evaluation boards come with 122.88 MHz VCXOs attached. However, I can confirm that both of your PLLs lock. I downloaded your configuration and tested it (albeit with different numbers for the first PLL, but with numbers that have the exact relationship as in your configuration) and found that both PLLs will lock. 

    I have attached the final configuration for good measure. Hope this helps.

    rfsoc_lmk4828.tcs

    Thanks,

    Michael