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Tool/software:
#1
W have 100MHz to CLKin1, By setting all devices in single loop 0 delay mode and using CLKout8 as FB CLK.
The Device Clock outputs are aligned without toggling PLL SYNC pin nor SPI SYNC.
However the SYSREF outputs are not.
I've enable the PLL2R_SYNC_EN, by toggling the pin HIGH then LOW as as 8.3.1.1, SYSREF are still not aligned.
#2
Would LMK04832 be able to have all Device Clock and SYSREF outputs aligned by toggling the PLL SYNC pin as 8.3.1.1?
Was there any Freq restrictions between Device Clock and SYSREF?
Hope to hear from you ASAP.
Hi new2day,
The SYSREF block shares the same path with the SYNC path.
In order to generate a SYSREF output you first need to SYNC the output dividers i.e. perform a sync event.
Page 30 of DS goes into detail on how to setup SYNC/SYSREF with an example in section 8.3.3.1.1
Could you share your block diagram or clock tree? A schematic and configuration file (.tcs) would be of great help.
Best regards,
Vicente
