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Tool/software:
Hi. I am trying to get a CDCM6208 working on a newly spun board. I used the CDCM6208 application and evaluation board to generate and verify settings, and it all seems to work without issue there.
On my own board, the loss of reference bit is always set in the status register (0x0006). I programmed the registers in order using the values from this application, and tried toggling the reset but in register 4.
My schematic looks like this:
I have verified that REF_SEL is high, and that a 10MHz reference signal is on pin 8. The reference looks good, a solid square wave, 0 to 3.3V. Powers supplies look good as well.
I tried various settings for the MUX, but none seem to have helped.
Any assistance would be greatly appreciated.
Hi Chris.
I have connected PRIREF_N to GND, but it didn't help. I have also read back all the registers and confirmed that your values were properly programmed into them.
Here is the part of the schematic you asked for:
The CSAC is an atomic clock providing a very stable, very accurate 10MHz. It is then buffered and REF_CLK2 is routed to the PRIREF_P input of the CDCM6208. Looking at it on my oscilloscope, it's a solid 10MHz square wave, 0-3.3V, very fast and square edges, no visible glitching etc. And as we confirmed, with bypass enabled we get a nice 10MHz output from the CDCM6208.
Paul,
One thing that I notice during testing is that, when supplying an LVCMOS input clock, if I change the input type to LVDS the PLL will lock (though the PLL will still show that there is no reference clock). This required AC-coupling the LVCMOS input on PRIREF_P.
Does this work on your custom board? Or is there no spot to add an AC-coupling capacitor?
Otherwise, we achieved lock with a single-ended LVCMOS input by connecting PRIREF_N to GND through a 0-ohm resistor. I also see this thread where Hao recommends AC-coupling PRIREF_N to GND with a 0.1uF capacitor for successful operation: https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1011981/cdcm6208-osc_25mhz-lvcmos-to-pin-8-pri_refp-pin-9-pri_refn-of-cdcm6208v1h-connection?tisearch=e2e-sitesearch&keymatch=cdcm6208%25252525252520lvcmos#
One potential issue is the loop filter - typical external loop filter configuration is as such (which does not quite match your loop filter schematic):
This may impact the locking of the PLL as well. Note the external loop filter connections on the evaluation module:
Thanks,
Kadeem
Paul,
Interestingly, when using your configuration, I get an output of 2.305MHz instead of 2.048MHz. But when I use the configuration I suggested earlier [reattaching below] I get the correct output.
I know we suggested some changes to your schematic, particularly the loop filter. I know you mentioned you changed the ELF values to match the EVM, but our main concern is the way the passives are connected.
In your schematic, the resistor is in series with the two capacitors, when it's only supposed to be in series with one capacitor. Was this change made as well? This can have unintended effects on device performance.
As for the VCO frequency, I will continue to look into this on the bench.
Best,
Cris
Hi Cris. I can't find a solution that results in an integer divider and which is in spec. The closest I can come up with for a V1 is this:
The VCO frequency is just outside the 2550MHz limit given in the datasheet. It's not ideal but I'm tempted to live with it, or replace the chip with a V2. I'm not keen on a fractional PLL divider.
That said, with those settings, it does seem to work, the LOS detector bug not withstanding.
