• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 20 subscribers
  • Views 473 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPL5000 base case

Joshua Stephens
Prodigy 10 points
Other Parts Discussed in Thread: TPL5000

I'm wondering if someone can set me straight and confirm or correct my design. I have the TPL5000 chip. I'm making a breakout board just to test in another circuit. I'm connecting D0,D1,D2,VDD and PGOOD all together and to 3.3V. I'm connecting DONE and GND to 0V. RSTn and TCAL are floating because I'm not interested in that right now. I'm expecting WAKE to get toggled on and then off every 64s. I'm not seeing any movement on the WAKE pin at all. Any ideas? Am I expecting the wrong thing, or must there be something wrong with my circuit/observations.

Thanks

  • 0
    TI__Genius 9655 points

    Hi Stephens,

    if you want to see the wake signal every 64 sec, the TPL5000 needs to receive a done signal. As explained in the DS, last sectionof the application note, you can implement your feature connecting the TCAL pin to the DONE pin. You can leave the RSTn floating.

    At power on of the TPL5000 you will not see the first WAKE pulse after 64s, but after 128s. This happens becasue after the power on the TPL5000 sends out a RST signal after the programmed delay elapses. It means that after power on you will see the following:

    Power ON -   64s delay - RST pusle - 64s delay - WAKE pulse - 64s delay -  WAKE pulse - .......

    I've assumed D0=D1=D2= VDD, PGOOD = VDD, TCAL=DONE, RSTn floating.

    regards,

    Domenico