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Role of jitter cleaner

Taeyeop Kwon
Prodigy 150 points
Other Parts Discussed in Thread: DAC34SH84, LMK04808

Hi,

I'm Kwon. There is a question about jitter cleaner.

I use THW30SH84EVM and LMK04808B(Low-Noise Clock Jitter Cleaner) is a part of it.

For DAC clocking, external signal of 1474.56 MHz from signal generator is configured.

If I adjust clock frequency a little(± 1 MHz), output signal does not change.

A litte change of clock frequency doesn't influence output signal frequency.

Is this the role of jitter cleaner?

Would you explain how jitter cleaner works in case of external signal frequency being changed slightly or normal case ?

Thank you.

Kwon.

  • 0
    TI__Mastermind 32575 points

    If you are using a ~1.47 GHz RF sinewave input to J12, you need to configure the LMK04800 part in "Clock Distribution" mode in the LMK04800 Control tab as discussed in Section 5.1 in the TSW30S84EVM user guide.  When in Clock Distribution mode, the LMK04800 functions as a clock fanout buffer with frequency division capability to distribute clocks for the FPGA (to TSW1400 via J13 connector), DAC34SH84 device (OSTR_CLK, DAC_CLK), and spare output SMA ports (J2/J3, J5).

    Per Section 3.4 in the EVM user guide, there are example files for configuring the EVM. 

    Click on LOAD REGS, browse to the installation folder, and load example files. The example files are located at C:\Program Files\Texas Instruments\TSW308x\TSW308xEVM_Configuration_Files\TSW30SH84_32bitLVDS_4Channel. To configure the LMK04808B in single PLL mode, select the file in the LMK04808 PLL Mode 10MHz reference folder. To configure the LMK04808B in clock distribution mode, select the file in the LMK04808 Clock Distribution Mode folder.

    In the TSW30S84EVM user guide, refer to section 2.2.4 for programming the LMK04800.  In Clock Distribution mode, you do not need to program the PLL-related registers the PLLs are not used in this mode.  Refer to the LMK04800 datasheet for information on Clock Distribution Mode, as well as Single PLL2 Mode, and Dual PLL (PLL1 + PLL2) Mode.

    Regards,
    Alan

  • 0 in reply to Alan O
    Prodigy 150 points

    Hi, Alan

    Thank you for your reply.

    There is no problem using TSW30SH84EVM with 'clock distribution mode'. It works well.

    My question is the role of 'jitter cleaner' .

    Is it possible that output clock frequency of jitter cleaner being fixed when that of input changing slightly.

     

    For example, input signal frequency of LMK04800 changes from 1 GHz fo (1 GHz  + 100 kHz)

    output signal frequency maintains 1 GHz(like PLL locking).

    This is experimental results. I expected to output frequency being changed, but it didn't.

    Is this phenomenon correct? If possible, because of  jitter cleaner ?

    Thank you,

    Kwon