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Hi,
I am trying to figure out if this part will work for me and I am having trouble figuring out how to calculate the possible frequencies it could supply. Looking at the datasheet on page 7, the diagram shows P (prescaler) and F (feedback divider) but then the main equation for finding the output frequency (equation 1) uses only F. This would indicate that F is meant to include P but the diagram shows them separately. Then, in equation 2, P is used without F so if F includes P in equation 1, how do you know what P is by itself?
Can anyone clarify this?
Russ
Hi Russ,
I have recently used a similar part CDCE62005 in one of my projects. It is similar to CDCE62002, and so possible my post will help you.
1. I used the CDCE62005EVM software which can be downloaded from TI's website. It gives an easy to use GUI to calculate frequencies and corresponding register values. I found the range of frequencies from this, but the register values didnt quite make the chip work.
2. The formula you mention above is similar to the one in CDCE62005 datasheet, and it has some discrepancy. I got a better explaination about it in one of the supplementary document of CDCE62005. So I feel a similar document for CDCE62002 should exist.
3. Although you get the divider/multiplier values from the GUI, I wold suggest you enter the register values referring to the datasheet rather than depending on the values provided by software, if your hardware is not the same as EVM.
In a nutshell, the software above will help you to bypass the confusion in the formula, and the discrepancy can be found in a similar supplementary document as the one existing for CDCE62005.
Hope this helps.
Regards,
Sid
Thanks for your input, Sid. I looked at the CDCE62005 as well and it does have the same confusing equations in the datasheet. I downloaded the evm software for it and tried that (although I don't have an evm) and it didn't really answer my question. I think that I just can't do what I want to do with it, although I didn't find a definitive answer on that.
I need a clock at 44.000MHz with the ability to change the frequency in very small steps of 1 KHz. As far as I can tell these parts cannot achieve that so I am looking at a DDS clock generator solution now.
Thanks,
Russ
Hi Russ,
Your application certainly needs a DDS clock generator. You can go for a small Spartan 3 FPGA which has a free DDS IP core from Xilinx. That can suffice your solution. Besides Spartan FPGA can also help you implement any logic which can help you save hardware on board as well.
Regards,
Sid
Hi Sid,
Thanks for the tip about the free IP core. I might look into that as we are using a Xilinx fpga in the design anyway, although it will be a Virtex5. Going that route still requires an external DAC though so I think it might be simpler to use a dedicated DDS chip (too bad TI doesn't have any). I have used an ADI part for this purpose in the past but I was hoping to find another solution that had better jitter performance.
Russ