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CDCE906 SMBus compatibility with I2C

Martin Emmerson
Prodigy 10 points
Other Parts Discussed in Thread: CDCE906, CDCE937, CDCE925, CDCE706, CDCE949, CDCE913

Hi All,

I am wondering if anyone has tried interfacing the CDCE906 device to a Cypress CY7C68013 USB device

I2C bus? The data sheet states the SMBus is based on I2C but what are the differences.

I am comparing a CDCE906 against a CDCE937 and CDCE925.

I am unable to communicate with the CDCE906 on the I2C bus but both the other devices work fine.

I am wondering if there is some subtle difference between the 906 SMBus and the I2C bus on the other devices?

All the devices are on similar plug in boards connecting to a common Cypress CY7C68013 USB chip SDA and SCL pins.

I have already increased the pull-up resistors on the I2C bus from 2k2 to 10K to the  3.3V rail, to conform to the 350uA

maximum current for the SMBus, but this made no difference.

I am supplying the 906 from a single 3.3V supply the same as that used for the other devices with the 1.8V supply not used for the 906.

Both pins 1 and 2 (S0 and S1) are tied high and I am addressing the device as 0x69 and 0x6D for the CDCE937 which works.

I notice on the data sheet for the CDCE906, page 11 shows Read (bit0) as active low! as page 12 shows it as active high like the CDCE937

I am assuming that this is an error in the 906 data sheet?

 

Thanks!

Martin.

  • 0 in reply to mapefer3
    TI__Expert 5725 points

    The CDCE906 and CDCE706 are both SMBbus communication type of devices. When using a uController that generates I2C protocol it might be that the timing between the SCK falling edge and the change of SDA is not respected for SMBbus but it is respected for I2C.

    Special care must be taken on the SDATA hold time that for the CDCE906 and CDCE706 is 0.3usmin and for the CDCE925, CDCE949, CDCE913 and CDCE937 is 0us min.

    Also to the START setup time is different for the CDCE906 and CDCE706 being 0.6us minimum as opposed to the  CDCE925, CDCE949, CDCE913 and CDCE937 4.7us min.

    The plot below was taken when using a AT91SAM9260 processor using TWI, the dark blue (top) trace is the data while the light blue (bottom trace) is the clock. You can see that the data is changing from 1 to 0.The time between the two falling edges is 30 ns (it should be at least 300 ns, as written in the datasheet), that caused the acknowledgement to be missing. That would be a not respected SDATA hold time, even using a AT91SAM9260 processor that generates TWI

    Please go to the following application note to debug I2C:

     http://focus.ti.com/general/docs/litabsmultiplefilelist.tsp?literatureNumber=scaa106