Part Number: CDCE62005
I am in the process of debugging a board that was built with the CDCE62005 clock generator IC. The IC is used to generate several clocks. At the moment, I am only debugging one of the clock outputs; a 400 MHz LVDS clock.
Earlier in the debugging process, I was able to get the clock generator to successfully output a 125 MHz, LVDS clock as a quick test. A primary input clock of 10MHz, which is divided by 2, is used as a reference clock.
When I attempt to generate the 400 MHz clock, I am not able to get the PLL to lock. Based on the divider parameters that I am using, the frequency of the VCO is 2 kHz, which suggests that the VCO should be set to the low range. However, clock frequency seems to be closer to 400 MHz if the high range is used instead.
I am using the internal loop filter. After seeing some previous posts concerning PLL lock and the values for the loop filter, I used Web Bench to generate a new set of resistor and capacitor values for the loop filter. However, I did not notice any change.
Here are the latest register values that I am using to set the 400 MHz clock. Note that I am first bringing up the clock generator to output the 125 MHz clock. A manual calibration is then initiated, which results in a PLL lock. Next, the registers are reconfigured for the 400 MHz clock and a manual calibration is then initiated. However, this does not result in a PLL lock.
Reg Value
0 E9 40 03 10
1 68 00 00 00
2 68 00 00 00
3 68 00 00 00
4 68 00 03 10
5 78 08 0F 00
6 80 FE 1B 80 (Set to 84 4E 1B 80 to begin manual calibration)
7 BC 04 7D 60
Any assistance would be much appreciated.
Thanks,
Todd
