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LMK04616: Ouputs architecture

Alex Zabrovsky
Prodigy 170 points
Part Number: LMK04616

Hello

I'm considering using the device for multi-stage clocking architecture utilizing several of these devices while the last stage will need to drive all 16 outputs independently (and perhaps differently configured frequencies and delays per each output).

From the datasheet I understand that each of these 16 outputs is individually configured for frequency (dividers after PLL2) and delays, i.e. all of 16 outputs are completely independent in configuration from each other.

However the diagrams in the section 9.4 (Figures 51 through 54) suggest that the outputs are boundled in pairs to 8 blocks, i.e. each block drives 2 adjacent differential outputs. The diagrams also suggest that the dividers/delays configuration is idividual for each block (not output), i.e. each two adjacent outputs share the same deviders/delays configuration. Is that correct ? If this is the case, the user cannot have 16 totally inpedentent outputs, but rather 8 independent pairs of differential outputs allowing up to 8 different frequencies and 8 different delay settings

AM I wrong ? Please advise

  • 0
    TI__Intellectual 2100 points

    Hey Alex,

    To start, let’s answer your question: you can get 16 independent diff clock signals out of this chip.

    Now let's explain what's going on. What you are seeing is the JESD204B compliance and functionality of this device. The JESD204B standard requires a device clock of the desired frequency and a SYSREF clock to function; every device requires a pair of clocks. In an effort to allow this device to support the JESD204B standard for eight devices the architecture has these eight blocks to allow for easier generation of the SYSREF signal for all JESD channels, of which you can have 8. If you don’t want to use the JESD204B standard in your devices however, you can program each of the 16 outputs for its own frequency as long as you don’t exceed the PLL locking parameters in the datasheet and keep similar frequencies together. Just ensure you don’t enable the SYSREF registers for JESD204B operation.

    You can see how they intended people to use the chip for JESD204B in the simplified schematic on page one of the datasheet (inserted below).  Each peripheral is getting two clocks, a device clock and SYSREF for fast JESD serial communication. However, you don't have to use JESD.

    It is worth a mentioning that if you want you can actually get 17 output clocks from this device if you want to use the buffered OSCout diff pair, completely up to you.

    If this answered your question correctly please hit the green “Verify” button below, plus I like knowing you guys and gals aren't still wavering on info. Let me know if you have any more questions and I’d be happy to help with those too!

    Best Regards,

    Nick

  • 0 in reply to Nicholas Mariani9
    Prodigy 170 points

    Thanks a lot Nick

    I understand the intention of TI to suggest the device in such way for easier JESD204B implementation.

    Pairing of the outputs in 8 groups indeed allows convenient way of DevClk/Sysref pairs formed by each of 8 blocks

    I'm looking into output block picture (Figure 24):

    I see only a single 16-bit divider that is shared by both CLKoutX and Y outputs. The only what is split per each of these outputs are delays.

    According to that, I still cannot get how one would program each of these outputs within a block to a different frequencies. We have single CLK input to the block, then single 16-bit divider that splits its output into two pathes of X and Y. How that would allow me to generate different frequencies on X and Y ?

    Once again, this is for the case I need 16 different frequencies so that each block would output 2 different frequencies..

    What do I miss ?

    And some more: I also posted another quesiton related to this device few days back that still is not answered. The quesiton relates to the HSDS/LVDS output voltage span defition as defined in teh datasheet...I'll appreciate if that can be handled as well...

    Best regards, Alex

  • 0 in reply to Alex Zabrovsky
    TI__Expert 8865 points

    Hello Alex

    Sorry for the delayed response.

    Like mentioned on the first page of the datasheet:

    16 Differential Output Clocks in 8 Frequency Groups

    – Each Output Pair Can be Configured to SYSREF Clock Output


    There are 8 dividers for 16 outputs. 2 adjacent outputs share a single divider. OSCout is additional output with separate divider.

    The delay programming is independent for each output. Please refer to the Block diagram in Fig 14 and single channel block diagram in Fig 24 of the datasheet.

    Don't hesitate to contact me if you have further questions.

    Best regards

    Puneet

  • 0 in reply to Puneet Sareen
    Prodigy 170 points

    Thanks

    So if using not for JESD but rather general clock generation/distribution, there are maximum 8 different frequencies that can be didstributed to 16 loads given each 2 outputs of same frequency is configured in the same block. This is my understanding.

    Now, for using for JESD, can I use each block to generate DevClk on X and Sysref on Y ? If requiring continuous or gapped-periodic Sysref, there must be frequency defined for Sysref as well.

    Lets say, have 50 MHz of DevClk and 1.5625 MHz of continuous Sysref. I understand because of having common divider in each block, I cannot put 50 MHz of DevClk on output X and 1.5625 MHz continuous (or gapped-periodic) Sysref on output Y in the same block. Rather then that, I need to saparate all the DevClk and Sysref to the saparate blocks, hence being able to run them at different frequencies.

    So that having to drive 8 JESD204B subclass 1 devices, I would need to configure 4 blocks (total 8 outputs) for DevClk and the rest of 4 blocks for 8 SYSREFs, thereby covering 8 JESD devices.

    Am I wrong ?

  • 0 in reply to Alex Zabrovsky
    TI__Expert 8865 points
    Hello Alex,

    You are right. Each channel consists of two outputs and one common divider. You cannot have two different frequencies from one channel. Like you mentioned, you will have to separate the device clocks and SYSREF clocks and generate them from different channels.

    Best regards
    Puneet
  • 0 in reply to Puneet Sareen
    Prodigy 170 points

    Thanks a lot, that clarifies