I use LMK01020 as the system clock, but spurious is out.
Please tell me how to reduce it.
We use it under the condition that
Input : 245.76 MHz, LVDS
Output: 245.76 MHz, LVPECL
Events occur that spurious of about -60 dBc (245.76 MHz ± 500 kHz, ± 1 MHz, etc.) is superimposed on the output signal.
A DCDC converter with a switching frequency of 500 kHz or 1 MHz is mounted in another place on the same board.
These DCDC converters are not convinced of spurious sources.
However, I want to challenge to reduce the spurious.
· Reduce spurious level of output frequency
· Improve power switching immunity
I would like to teach you if there is any policy to do so.